How to avoid C4 violation in Synopsys DFT compiler

all_fanout comand design compiler

Hi,
I am using Synopsys DFT compiler for Scan Insertion in XG Mode. During Pre and post design rule checks I am facing C4 'rst not able to Capture Data while other clocks are Off' violation.

I am declaring my reset port like this :

set_dft_signal -type reset -port rst -active_state 1

I am using the autofix like this
set_dft_signal -type TestData -port rst
set_dft_signal -type TestMode -port test_mode
set_autofix_configuration -type reset -test_data rst

I am able to clear all the violations mentioned in Pre dft_drc stage except this C4 violation.

I don't have any GUI facility. Thus, I am unable to trace this error visually.

Can someone help me in clearing this violation?? I shall be very glad if I can get the solution immediately as I am stuck up at this point right now.

Thanks in advance

Regards,
S.Nikhil

dft drc

Hi Nikhil,

First thing you cannot get C4 in the pre_dft drc, it will be some D violation.

Second, you have not used the command

set_dft_configuration -fix_reset enable ( may be you miss to write that here)

Further, I dont think that autofix will solve this problem. It is a capture issue and not scan shift issue. What I think is happening here is that , your reset pin before reaching the flop is gated with testmode and then reaches the flop. The flops are not failing the drc and coming on the scan chain because the reset on the pin of the flops is in inactive state.

You can trace the top level reset pin in your design to see if it is getting gated some where.


In DC you can use the command

all_fanout -from reset

-cheers
vlsi_eda_guy

set_dft_configuration -fix_bus enable

vlsi_eda_guy is mostly correct. The pre-insertion dft_drc result will be a D2 (set) or D3 (reset) violation. By default, fixing sets and resets are not on by default.

However, I think that fixing these WILL solve your problem. A "fixed" reset will properly be disabled when shifting through the flop, allowing it to be inserted onto the scan chain. Fixing can be accomplished with a MUX or a GATE (with Scan Enable). You might have a look at the DFT Compiler User Guide chapter on "Using Autofix" found here:

https://solvnet.synopsys.com/dow_retrieve/A-2008.03/dftxg1/dftxg1_architecture_adv.html

Please send future Synopsys product support questions to support_center@synopsys.com.

Best regards,

Adam Cron, Synopsys

synopsys dft

Adam,

Welcome to Forum.

The violation C4 corresponds to D8 in pre_dft. No we cannot fix D8 with autofix.

#It does not violate any cells but can lead to C4 violations is post-DFT DRC

It is very clear that the violation is for the clock and not for a flop.

-cheers
vlsi_eda_guy

synopsys

Hi vlsi_eda_guy,

Thx for ur valuable information. It is indeed D8 violation at the pre dft drc stage and I did use set_dft_configuration fix_reset enable cmd as part of the autofix.

Moreover, when I did observe the fanout of the reset, it indeed is getting gated in the design.

Now, I am trying to bypass this gated logic of rst manually by inserting a mux with one input of mux as rst and other input as gate output and the test mode signal as the select line of mux and then connect the mux output to the flop rst pin. Is it okay to do this. Can this solve the C4 violation.

If you have any other solution, plz suggest me.

thanks in advance

S.Nikhil

violation in synopsys

Hi Nikhil,


Yes that is the way you have to fix it.
BTW why there is a gating logic on the reset. If it was inserted by DFT COmpiler during insert_dft then you need to tell the tool to use the mux for fixing reset also.

To remove C4 violation all we have to make sure is that if we pulse the reset at the flop should get reset.


-cheers
Anand

PS: Did I help you ;-)