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Testability issues in sequential circuit

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cfreng2

cfreng2

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Hi all! I just want to ask what are the testability issues in a sequential circuit? Say you are given a sequential circuit, what testability issues you can discuss on that sequential circuit?
 

hi.....
If ur question is related to DFT....then we have a problem of controlability and observability in a sequential ckt........for making a sequential ckt testable we use scan chain concept....in which we use shift operation for controlabilty and cloking and serial shift out for observability..........
 

    cfreng2

    cfreng2

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Yes in dft the sequential circuits are not scan able so we can't control and observe them .to meke them scanable we convert that sequential circuits into scan able flops by giving input through mux.
 

    cfreng2

    cfreng2

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thanks for your help.
 

Hi,

The state of the sequential ckts are not controllable and observale. Thus, they are converted to scan flops by adding a mux before the normal flop. Now the internal states of these scan flops are easily controllable and observable and even accessible through the series of shift registers (scan chains).

Now, you can get the scan flops into the reqd states, and then shift in, capture, update the outputs of the flops.


thx
snr_vlsi
 

Well, we can covert the normal flops into scan flops and then make a chain out of it to get the controllability and observablitly for a sequential circuit.

Putting these flops on the scan chain itself can be challenge if you don't plan for the DFT at the starting of the project.

The clock and reset should be controllable from the top for the flops which you want to put on the scan chains.

Apart from this there are a number of capture violations, which effects your coverage even though all the flops are on the scan chains. For example Leading edge flop to trailing edge flop connection. This can be a valid connection in functional mode, but it can impose coverage issues another issues are like, clock as data etc...
 

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