Subthreshold folded cascode Opamp

Subthreshold Opamp

I'm trying to design a low power subthreshold opamp.
I have some doubts about it. Plz help me out.
1) Is it passible(acceptable) to bias all first stage transistors in subthreshold.
2) if yes, what is the criteria to decide W/L of M3 & M4.
3) i have solved expression of Av for diff amp in subthreshold region. the outcome is, gain independent of current and W/L. is there something wrong.

Av=gm1/(rds2||rds4) --- gain of diff ampli.(independent of Id & W/L)

gm = Id/n*Vt ---- in subthreshold

rds ≈ 1/ λ* Id
after solving gain comes

Av= 1/ n*Vt(λN+λP) --- if we solve it it comes very high.

Whatever i have taken it gives very small gain (by simulation), less than 1
pls, tell me how i can decide w/L of M3 & M4.
Thanks in advance.

Subthreshold Opamp

1. You do not want current mirror active loads to be in subthreshold because any mismatch between M3 and M4 would cause a higher current mismatch because of the exponential relation of the subthreshold biasing. So, M3 and M4 should be in saturation if you can help it.
2. M3 and M4 should have a Vgs - Vth >= 150mV (higher is better); drop across (i.e. Vgs of) M3 should not be high so as to put M1 in the triode region, i.e. M3 and M4 should be sized so as to give the high common mode input voltage.; There are other criteria such as high output impedance of M4, minimal Cgs of M3 and M4 so that it does not play a role in bandwidth, etc.
3. I agree with your analysis and you get a gain independent of W/L. However, keep in mind that you need a high W/L to put the input pairs in subthreshold for a given Id. And, thus the gain DOES depend on W/L. Also, the lambda in your rds equation depends on the channel length (L) of M3 and M4.

In your simulation, please check to make sure that the transistors are biased correctly and that the current mirror loads are all in saturation and input pairs are in subthreshold/weak-inversion.

Subthreshold Opamp

hi transbrother,
I agreed with ur ans. I have seen one research papaer in which current loads are biased in saturation. But as the input pairs are in subthreshold they have current of 55nA. Is it possible to flow same current thro M3 & M4 while they are in saturation.
Thanks for ur reply. Tell me more......

Re: Subthreshold Opamp

amitjagtap said:

I'm trying to design a low power subthreshold opamp.
I have some doubts about it. Plz help me out.
1) Is it passible(acceptable) to bias all first stage transistors in subthreshold.
2) if yes, what is the criteria to decide W/L of M3 & M4.
3) i have solved expression of Av for diff amp in subthreshold region. the outcome is, gain independent of current and W/L. is there something wrong.

Av=gm1/(rds2||rds4) --- gain of diff ampli.(independent of Id & W/L)

gm = Id/n*Vt ---- in subthreshold

rds ≈ 1/ λ* Id
after solving gain comes

Av= 1/ n*Vt(λN+λP) --- if we solve it it comes very high.

Whatever i have taken it gives very small gain (by simulation), less than 1
pls, tell me how i can decide w/L of M3 & M4.
Thanks in advance.

Click to expand...

Hi Amit,
which process or technology it is ? and how do u get λN,λP, Kn, Kp is this through set of simulations? how much was there difference u see for your technology from the hand calculation to the actual

Subthreshold Opamp

hi Kumar
I'm using tsmc 0.25um Technology. and all parameters are taken form technology file. Lambda is not included in techno file thus it is calculated approximately by plotting id Vs Vds curves.

Re: Subthreshold Opamp

For an drain of 55nA, you are probably right in saying that it will be hard to bias the current mirror loads in saturation (unless you make their W/L really small in order to maximize Vgs). My question is whether a 55nA of current makes sense for an input pair of an op amp? You are getting close to the leakage of the devices....On the other hand, is it a possibility to increase the current thru the input pairs (to say 1uA) and have a high W/L to put them in subthreshold. That way you have more room to play with in order to keep the current mirror loads in saturation.

hope this helps.

Subthreshold Opamp

Hi transbrother,
whatever ur saying is correct. I'm thinking of increasing the current to 80 to 100nA.
But still the W/L is very low. Less than one. is it acceptable. Another thing is how i can calculate or estimate the leakage current of the transistor where the is that subthreshold current it self treated as leakage current of the device.
Do you want to say that this small 55nA current is above some accetable level or not? is it ? I think yes. waht do you think.
tell me plz.......

Re: Subthreshold Opamp

55nA is in my opinion a bit low for the drain current of your input pair because your other op amp parameters such as slew rate is going to degrade. What is restricting you to put that low a current for your input pair.

I think it is a fair assumption that leakage can be like 1nA - 10nA depending on the process. Of course, some proceses can be lower than that and some higher. You should take a look at the process manual to see how much it can be.

the w/l for the active load can be much lower than 1; but how much lower than 1 is it? Is your area so large that your bandwidth is getting affected?

Subthreshold Opamp

hi transbrother,
I'm designing a low power opamp,this is limiting factor for the current. Well mostly all market low power opamps have low slewrate and bandwith.
W/L i got is 0.3. I selected L=5um & W=1.5um. Is it OK.
I got UGB of 7Mhz of first stage.
if u have any suggestion on this... plz let know.

Re: Subthreshold Opamp

I do not see any problems with a W/L = 0.3 as long as your other op amp parameters are not affected.
However, I would check the process manual for leakage currents for the dimensions you are dealing with.

Subthreshold Opamp

HI Transbrither,
Thanks.
what i have seen from mosis tsmc0.25 technology file is that minimum W/L is 0.36/0.24 , then in the case of W/L < 1 is it neccesary to chose minimum W and then calculate respective L.
Another thing is this, for greater Vgs i got w/L arround 0.08. Thus i kept Vgs just above Vt. Is it Ok.
Thanks again

Subthreshold Opamp

hi transbrother,
Can u tell me where i will get process manual of TSMC0.25 technology.

Re: Subthreshold Opamp

Your W/L is not too high ,contrarily i think this is too "LOW".
Transistor operation in subthreshold the Vgs-Vt must small to correctly enter that region.
you can refer some books , the subthreshold condition is Vgs ≈Vt or even below Vt.
So you can enlarge your W/L ratio to decrease Vgs-Vt (if current is constant).
then check input transistor's operating region.

Re: Subthreshold Opamp

I believe if you go to mosis.com you can find the tsmc 0.25um process. Do, check papers on leakage currents Vs device geometry for deep submicron processes. That should give you a good idea.

I would recommend against making min. W because you'll have to deal with Width offset when you fabrcate these devices. you wont get good matching when you have W min. Instead, you can choose an arbitrary W =1 and thus L = 12.5 or how much ever you need it to be. a W/L of 1/12.5 is not unheard of and especially if your strict requirement is to make the input pairs operate at 100nA, you probably doesnt have any choice.

hope this helps.

Subthreshold Opamp

hi transbrother,
In the case of w/L < 1, My teacher said it is not acceptable.
Do you any design document (PDF) which have got W/L < 1. So that i can show them it as a proof. Its very important issue of my design plz help me.
waiting for ur reply.

Subthreshold Opamp

Hello amitajaptap,
Could you please ask your teacher to explain to why W/L < 1 is not acceptable? There must be a reason.
Take for e.g.
**broken link removed**

In this file they have a 1/4 current mirror.

May be you should ask your teacher, how he/she proposes to get enough vgs drop across the current mirror loads by not making a low W/L ratio.

Subthreshold Opamp

hi transbrother,
Yes i will. I also got one document which have W/L < 1.
Thanks for the link you have send, its good.