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Successive Approximation ADC

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firsttimedesigning

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verilog code for sar

So I am desingning a SA ADC. The problem I am having is that how can I design the Successive Approximation Register (SAR). Do I design it using state diagrams?
If I use state diagrams (Moore State) to design it, then I will have to draw A LOT state diagrams for a SA ADC that can convert 8 bits. State diagrams is the only way that I know, is there any other way?
 

successive approximation adc

you can use an old implemention

Added after 11 minutes:

try data converter book there are many in forum
 

sar adc basics

Refer to Allen's book, in the charpter of ADC, there is a perfect diagram of SAR ADC, just do as that diagram!
 
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    sijil

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sucessive approximation

do you hAVE ALInk to it arsenal
 

sar verilog code

SA register can be made as a simple shift register which shifts a logic HIGH from MSB flop to LSB flop. Also it stores the current comparator input to the corresponding flop.
This should be very easy to implement.. either writing VHDL code or manual design...
 

sa successiv approximation

allen's book for a start
 

successive approximation register verilog code

Hai

i had wriiten a code in verilog? but for better accuracy i think i need to go for analog design do u think may i right?
 

state machine+successive

The Successive Approximation Register can be designed entirely in digital ... no need to do anything in analog..
 

sar adc book

this book from analog devices will help u with the basics

h**p://rapidshare.com/files/53248394/3-09091.zip
(dont forget to put 't' in place of '*')

Added after 36 minutes:

also check these books....

Analog Circuit Design: High-Speed A-D Converters,

http://mihd.net/s9rqgj

Added after 12 minutes:

Data Converters

**broken link removed**

pass:gigapedia.org
 

analog circuit design plassche rapidshare

the password does not work... seems u have changed it...?
 

successive approximation adc converter

It can be disgned first in P-Spice
 

sar verilog program

Hey, you get videos on web teaching SAR-ADC design. In fact, Maxim-ic, National Semiconductor and Analog Devices provide application notes on SAR-ADC.
 

sar verilog program

There is no need for state machine if u know about how many cycles conversion takes place. u can generate the sample signal by delay elements(F/Fs) and use shift registers to transfer 1 from MSB F/F to other F/F for every conversion cycle. and latch the compartor output by generating the latch clock.
 

sar verilog code

Have any design example for SAR ADC?
 

sar code in verilog

search im this site
 

sar adc verilog code

try "CMOS Analog to digital and Digital to Analog converters" by Rud van Plassche.....u get basic ideas...also u get information about good reference papers on SA ADCs
 

sar adcs basics

When I design ADC (any type) for algoritm or logic I use verilog code. And for SAR you mast have not only 1 reg. Your logic bloc must contain driver for S/H, driver for Comparator and DAC. Realize this functions in primitive logic components not use VERILOG is difficult.
 

sucessive adc

” Data Converters

**broken link removed**

pass:gigapedia.org“

it's a very good book ,thank you！arjun_p_cet
 

successive approximation register verilog codes

see this papaer
"nonredundant successive approximation register for A/D converters"
A.Rossi and G.Fucili.
definatiley it wud help u.
regards
 

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