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How to convert VHDL code to Verilog?

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sameem_shabbir

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I have found some useful code regarding my project
But it is in VHDL
& I m a verilog user
how to convert it
or is there any other way that i should make some alterations in that code
 

verilog to vhdl wrapper

There are commercial tools out there that allow unidirectional/bidirectional conversions, however, the byproduct/result is not clean. The best approach to do this is to keep the original VHDL sources and treat them as a black box and all you need to do is write a Verilog wrapper around the top level function. All the synthesis and simulation tools are now capable of supporting both languages simultaneously.

Cheers,
-S
 

free verilog to vhdl translator

Hi! i found a useful verilog code for my project, but i'm a vhdl user. I know that the Xilinx Webpack what i'm using support both verilog and vhdl.
But i would like to understand the all code,please, can anybody translate it for me.
it is not a long code. Even if the part of this code will be translated, i'll appreciate, thank you in advance.

// sync SCK to the FPGA clock using a 3-bits shift register
reg [2:0] SCKr; always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
wire SCK_risingedge = (SCKr[2:1]==2'b01); // now we can detect SCK rising edges
wire SCK_fallingedge = (SCKr[2:1]==2'b10); // and falling edges

// same thing for SSEL
reg [2:0] SSELr; always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge

// and for MOSI
reg [1:0] MOSIr; always @(posedge clk) MOSIr <= {MOSIr[0], MOSI};
wire MOSI_data = MOSIr[1];

//Now receiving data from the SPI bus is easy.

reg [2:0] bitcnt; // we handle SPI in 8-bits format, so we need a 3 bits counter to count the bits as they come in
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;

always @(posedge clk)
begin
if(~SSEL_active)
bitcnt <= 3'b000;
else
if(SCK_risingedge)
begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], MOSI_data}; // implement a shift-left register (since we receive the data MSB first)
end
end

always @(posedge clk) byte_received <= SSEL_active && SCK_risingedge && (bitcnt==3'b111);

// we use the LSB of the data received to control an LED
reg LED;
always @(posedge clk) if(byte_received) LED <= byte_data_received[0];

//Finally the transmission part.

reg [7:0] byte_data_sent;

reg [7:0] cnt;
always @(posedge clk) if(SSEL_startmessage) cnt<=cnt+8'h1; // count the messages

always @(posedge clk)
if(SSEL_active)
begin
if(SSEL_startmessage)
byte_data_sent <= cnt; // first byte sent in a message is the message count
else
if(SCK_fallingedge)
begin
if(bitcnt==3'b000)
byte_data_sent <= 8'h00; // after that, we send 0s
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
end

assign MISO = byte_data_sent[7]; // send MSB first
// we assume that there is only one slave on the SPI bus, so we don't bother with a tri-state buffer for MISO
// otherwise we would need to tri-state MISO when SSEL is inactive

endmodule
 

how 2 write a vhdl wrapper over verilog module

sabres,

The Verilog logic is very simple serial to parallel conversion (8-bit in this case) which entails a start/end enable pulse, 3-bit binary counter, and an 8-bit serial to parallel shift register. Why don't you just re-code it to VHDL or simply create a black-box around the Verilog source and use the source as is. I have done lots of designs using both Verilog and VHDL, where Verilog is much simpler to understand/read/follow. If you know VHDL very well, the Verilog logic should be a breathe.

Cheers,
-s
 

how to create a verilog wraper for vhdl design

unfortunatly i'm not very well in vhdl :) but i know it better than than the Verilog.
what i know is asm and c on PIC microcontrollers.
What i have to do is a SPI communication between a PIC18f and an Fpga. And of course a have problem with the fpga's part of the communication.

I know what you mean, using the verilog code like a black-box. it's a good idea, but i don't want to use in this case.
Now i'm trying to rewrite that code in VHDL. i'm beginner in this hdl area so any help with vhdl code for a simple spi implementation or a translate of this code will be appreciated.

snowfall: thanks for your answer :)
 

module spi_slave

use the tools vhdl to verilog
but the style is not so well
 

vhdl shift register edge detection

i was serchin' for a while at google but i didn't find any free useable tool for VHDL to Verilog convert.

Can anybody give me a link for a free , working tool.it will be appreciated, thanks
 

vhdl to verilog wrapper vectors

sabres said:
Hi! i found a useful verilog code for my project, but i'm a vhdl user. I know that the Xilinx Webpack what i'm using support both verilog and vhdl.
But i would like to understand the all code,please, can anybody translate it for me.
it is not a long code. Even if the part of this code will be translated, i'll appreciate, thank you in advance.

// sync SCK to the FPGA clock using a 3-bits shift register
reg [2:0] SCKr; always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
wire SCK_risingedge = (SCKr[2:1]==2'b01); // now we can detect SCK rising edges
wire SCK_fallingedge = (SCKr[2:1]==2'b10); // and falling edges

// same thing for SSEL
reg [2:0] SSELr; always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge

// and for MOSI
reg [1:0] MOSIr; always @(posedge clk) MOSIr <= {MOSIr[0], MOSI};
wire MOSI_data = MOSIr[1];

//Now receiving data from the SPI bus is easy.

reg [2:0] bitcnt; // we handle SPI in 8-bits format, so we need a 3 bits counter to count the bits as they come in
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;

always @(posedge clk)
begin
if(~SSEL_active)
bitcnt <= 3'b000;
else
if(SCK_risingedge)
begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], MOSI_data}; // implement a shift-left register (since we receive the data MSB first)
end
end

always @(posedge clk) byte_received <= SSEL_active && SCK_risingedge && (bitcnt==3'b111);

// we use the LSB of the data received to control an LED
reg LED;
always @(posedge clk) if(byte_received) LED <= byte_data_received[0];

//Finally the transmission part.

reg [7:0] byte_data_sent;

reg [7:0] cnt;
always @(posedge clk) if(SSEL_startmessage) cnt<=cnt+8'h1; // count the messages

always @(posedge clk)
if(SSEL_active)
begin
if(SSEL_startmessage)
byte_data_sent <= cnt; // first byte sent in a message is the message count
else
if(SCK_fallingedge)
begin
if(bitcnt==3'b000)
byte_data_sent <= 8'h00; // after that, we send 0s
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
end

assign MISO = byte_data_sent[7]; // send MSB first
// we assume that there is only one slave on the SPI bus, so we don't bother with a tri-state buffer for MISO
// otherwise we would need to tri-state MISO when SSEL is inactive

endmodule
Click to expand...

Where is the beginning of the SPI module declaration?

To keep the translator happy, the entrance code have to be error free.
 

create vhdl wrapper for verilog

Where is the beginning of the SPI module declaration?

To keep the translator happy, the entrance code have to be error free.
Click to expand...

You're right. Here is the module decl:

module SPI_slave(clk, SCK, MOSI, MISO, SSEL, LED);
input clk;

input SCK, SSEL, MOSI;
output MISO;

output LED;

But what i need right now is a translation of this code to vhdl language. Or a translator, because i didn't find any free, useable translator.
 

led snowfall with microcontroller

Hello,

basically I agree with snowfall's suggestion to instantiate verilog modules as a component in VHDL, you wouldn't need a particular wrapper in most cases. As an issue, some tools may need an extra mixed-language license option to do this (I think, ModelSim). But Altera, Xilinx, whatever webtools can do.

If you need to modify the code somehow to adapt it to your application, you have to understand it's operation anyhow. I can't see, that Verilog is totally different from VHDL. I'm mostly using VHDL by tradition, but started Verilog for some projects on customers demand. To my opinion, it keeps you mentally agile, the same as learning natural languages.

Perhaps we can help you in converting some constructs that aren't easy understandable. As a basic difference, VHDL is more typified and also structurized(and thus more verbose - or long-winded).

I start with the synchronous edge detection:
Code: 
// sync SCK to the FPGA clock using a 3-bits shift register 
reg [2:0] SCKr; always @(posedge clk) SCKr <= {SCKr[1:0], SCK}; 
wire SCK_risingedge = (SCKr[2:1]==2'b01); // now we can detect SCK rising edges 
wire SCK_fallingedge = (SCKr[2:1]==2'b10); // and falling edges
In VHDL you have a strict separation of declaration and procedural part, you can't mix these as done in the Verilog example. Thus the statements have to be fitted into an overall structure:
Code: 
-- SCK : IN STD_LOGIC; -- defined in PORT, not shown here
SIGNAL SCKr : STD_LOGIC_VECTOR(2 downto 0);
-- if defined as STD_LOGIC, additional conversion function would be necessary
SIGNAL SCK_risingedge: BOOLEAN;
SIGNAL SCK_fallingedge: BOOLEAN;

BEGIN
  PROCESS(clk)
  BEGIN
    IF RISING_EDGE(clk)
      SCKr <= SCKr(1 downto 0) & SCK;
    END IF;
  END PROCESS;
  SCK_risingedge <= SCKr(2 downto 1) ="01";
  SCK_fallingedge <= SCKr(2 downto 1) ="10";
END;
I tried a "word-by-word" translation to emphasize the equivalence of constructs, different coding styles could be used.

Regards,
Frank
 

verilog code for spi bus

sameem_shabbir said:
I have found some useful code regarding my project
But it is in VHDL
& I m a verilog user
how to convert it
or is there any other way that i should make some alterations in that code
Click to expand...

You can use XHDL.
 
xilinx mixing vhdl and verilog

----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL
-- Sat Jan 26 10:27:07 2008
--
-- Input file : spi.v
-- Design name : SPI_slave
-- Author :
-- Company :
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--

PACKAGE SPI_slave_pkg IS
COMPONENT SPI_slave
PORT (
clk : IN bit;
SCK : IN bit;
MOSI : IN bit;
MISO : OUT bit;
SSEL : IN bit;
LED : OUT bit);
END COMPONENT;
END SPI_slave_pkg;


ENTITY SPI_slave IS
PORT (
clk : IN bit;
SCK : IN bit;
MOSI : IN bit;
MISO : OUT bit;
SSEL : IN bit;
LED : OUT bit);
END ENTITY SPI_slave;

ARCHITECTURE translated OF SPI_slave IS


-- sync SCK to the FPGA clock using a 3-bits shift register
SIGNAL SCKr : bit_vector(2 DOWNTO 0);
SIGNAL SCK_risingedge : bit; -- now we can detect SCK rising edges
SIGNAL SCK_fallingedge : bit; -- and falling edges
-- same thing for SSEL
SIGNAL SSELr : bit_vector(2 DOWNTO 0);
SIGNAL SSEL_active : bit; -- SSEL is active low
SIGNAL SSEL_startmessage : bit; -- message starts at falling edge
SIGNAL SSEL_endmessage : bit; -- message stops at rising edge
-- and for MOSI
SIGNAL MOSIr : bit_vector(1 DOWNTO 0);
SIGNAL MOSI_data : bit;
--Now receiving data from the SPI bus is easy.
SIGNAL bitcnt : bit_vector(2 DOWNTO 0); -- we handle SPI in 8-bits format, so we need a 3 bits counter to count the bits as they come in
SIGNAL byte_received : bit; -- high when a byte has been received
SIGNAL byte_data_received : bit_vector(7 DOWNTO 0);
-- we use the LSB of the data received to control an LED
SIGNAL byte_data_sent : bit_vector(7 DOWNTO 0);
SIGNAL cnt : bit_vector(7 DOWNTO 0);
SIGNAL MISO_xhdl1 : bit; -- send MSB first
SIGNAL LED_xhdl2 : bit;

BEGIN
MISO <= MISO_xhdl1;
LED <= LED_xhdl2;

PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
SCKr <= SCKr(1 DOWNTO 0) & SCK;
END IF;
END PROCESS;
SCK_risingedge <= TO_BIT(SCKr(2 DOWNTO 1) = "01") ;
SCK_fallingedge <= TO_BIT(SCKr(2 DOWNTO 1) = "10") ;

PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
SSELr <= SSELr(1 DOWNTO 0) & SSEL;
END IF;
END PROCESS;
SSEL_active <= NOT SSELr(1) ;
SSEL_startmessage <= TO_BIT(SSELr(2 DOWNTO 1) = "10") ;
SSEL_endmessage <= TO_BIT(SSELr(2 DOWNTO 1) = "01") ;

PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
MOSIr <= MOSIr(0) & MOSI;
END IF;
END PROCESS;
MOSI_data <= MOSIr(1) ;

PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (NOT SSEL_active = '1') THEN
bitcnt <= "000";
ELSE
IF (SCK_risingedge = '1') THEN
bitcnt <= bitcnt + "001";
byte_data_received <= byte_data_received(6 DOWNTO 0) & MOSI_data; -- implement a shift-left register (since we receive the data MSB first)
END IF;
END IF;
END IF;
END PROCESS;

PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
byte_received <= (SSEL_active AND SCK_risingedge) AND TO_BIT(bitcnt = "111");
END IF;
END PROCESS;

PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
--Finally the transmission part.

IF (byte_received = '1') THEN
LED_xhdl2 <= byte_data_received(0);
END IF;
END IF;
END PROCESS;

PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (SSEL_startmessage = '1') THEN
cnt <= cnt + "00000001"; -- count the messages
END IF;
END IF;
END PROCESS;

PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (SSEL_active = '1') THEN
IF (SSEL_startmessage = '1') THEN
byte_data_sent <= cnt; -- first byte sent in a message is the message count
ELSE
IF (SCK_fallingedge = '1') THEN
IF (bitcnt = "000") THEN
byte_data_sent <= "00000000"; -- after that, we send 0s
ELSE
byte_data_sent <= byte_data_sent(6 DOWNTO 0) & '0';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
MISO_xhdl1 <= byte_data_sent(7) ;
-- we assume that there is only one slave on the SPI bus, so we don't bother with a tri-state buffer for MISO
-- otherwise we would need to tri-state MISO when SSEL is inactive

END ARCHITECTURE translated;
 

verilog generater wrapper to vhdl

Hello,

thank you for demonstrating the tool. At least with this example, the result seems equivalent to a manual translation as I did for a snippet.

Regards,

Frank
 

write vhdl wrapper from verilog

Thank You :) I appreciate th'.

Regards , Sabres
 

vhdl sync code detection

the software I can strongly recommend is the X-HDL3, that might help you to save much time.
 

vhdl verilog wrapper

serach in forum there r free tools available.
 

Re: VERILOG --> VHDL

we are using xilinx ise 9.1. one of the module in our code is in vhdl ....all other modules in the project are .v files..... what can i do with the vhdl code?
 

Re: VERILOG --> VHDL

There's no problem in mixing the languages with Xilinx ISE, Altera Q.uartus or other recent design compilers.
 

Re: VERILOG --> VHDL

SynaptiCAD has VHDL to Verilog and Verilog to VHDL translation tools. They can be found at https://www.syncad.com/hdl_translators.htm . Several comments have mentioned that the translation tools produce messy results, mostly because there is not a one-to-one correspondence between the languages. SynaptiCAD has tried to address this problem by making it easier to navigate between the original code and the translated code, and by making it easier to compare test results between the models. Also when a section of code cannot be translated for some reason and needs human intervention, the translator puts in a large comment block and writes out all the information that it can figure out on its own. SynaptiCAD also provides translation services for those that don't want to learn all the differences in the languages.
 

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