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PVT conditions for worst case and best case analysis

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vlsi_deepa

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Hi,
1.For Worst Case Analysis,We are giving Less Voltage and Higher Temperature...
For Best Case Analysis,We are giving High Voltage and Lower Temperature...
But in both Cases We are giving Same Process Value (P=1)...

Can anybody tel me,
a.Wat is Process?
b.Why we are not Changing the Process value?

2.For Setup analy,We are using Worst Case PVT and
For Hold anal,We are using Best Case PVT....
WHY?


Thanks and Regards,
Deepa...
 

Re: PVT Conditions

Deepa,

Here is the soluions

At Launch clock path: Late clock, max delay in clock path, late derating, WC OC.
At Data path: Max delay, WC OC, late derating.
At Capture clock path: Early clock, min delay in clock path, WC OC. early derating

Slew propagation: max slew is propagated during setup analysis and min slew propagated during hold analysis.

Santhosh
 

Re: PVT Conditions

They do change. They are already included in the spice models from which the library characterization is done. The slow .lib includes one process corner and the fast .lib includes the other process corner.
 

Re: PVT Conditions

Hi rajesh9999,
Thanks for ur reply.... I have seen my lib file.. They are givin same Process Value for both Slow and Fast Lib.....
:cry:

Can u clearly explain me,Wat is Process? and In Which cases they are Givin Same Process value for both Worst and Best Cases?

Thanks,
Deepa...
 

PVT Conditions

process is the length of the channel of MOS used in the fabrication... the process doesnt change because it is fixed but the corner might change due to supply and temperature... the fast corner is high voltage low temperature condition in which the response is fast and hence it is the best case.....
 
Re: PVT Conditions

yes, anand explained it better.
 

Re: PVT Conditions

But suppose if we are working on 130nm still process parameter is set to 1 ? does it some how related to W/L ratio of transistor.Means L is constant but W can vary so is this showing this variation?Means my question is that why we put it between 0 to 1
 

Re: PVT Conditions

A.Anand Srinivasan said:
process is the length of the channel of MOS used in the fabrication... the process doesnt change because it is fixed but the corner might change due to supply and temperature... the fast corner is high voltage low temperature condition in which the response is fast and hence it is the best case.....
Click to expand...

You mean to say that if you are working in 130nm, no mosfet in a design can have a channel lenghth other than 130nm? Is this what you are trying to say? If it is, then its not a convincing answer.
 

Re: PVT Conditions

L is usually NOT allowed to change, only W is allowed to changed in standard cells. L is fixed at the minimum feature length, for example 130 nm in 130 nm process (Not exactly but a littlle higher for reliability and other robusttnes reasons). One can have special case cells where L is allowed to be changed (for example for low leakage cells). There is no advantage to be gained by allowing L to change. It will only make cells slower.

***************************

I believe, in some ways PVT are not 3 indepedent variables but P is indirectly related to V and T (spice simulations for delay calculations are done by varying V and T so it ooks like P has two cases, best and the worst while the variation in delay is actually due to changing Vand T) therefore the confusion. If some one has a different explanation or differring view, please do share it.

Thanks
 

Re: PVT Conditions

my answer is that the process tab is given 1 because we assume that the W and L we have given is exactly obtained in the chip... say if the manufacturer is sure that there would be variation and everything we have given would be 1.05 times larger than what we have given then it would be 1.05 but the exact dimension is hard to obtain even after fabrication...
 

Re: PVT Conditions

A.Anand Srinivasan said:
my answer is that the process tab is given 1 because we assume that the W and L we have given is exactly obtained in the chip... say if the manufacturer is sure that there would be variation and everything we have given would be 1.05 times larger than what we have given then it would be 1.05 but the exact dimension is hard to obtain even after fabrication...
Click to expand...

Thats what i wanted to hear.

Process is normally followed by a multiplier. This scaling factor accounts for variations in the outcome of the actual semiconductor manufacturing steps, typically 1.0 for most technologies. The multiplier is a floating-point number from 0 through 100. So actaully its not L but a factor accounting for its variation.
 

Re: PVT Conditions

onlymusic16 said:
Thats what i wanted to hear.

Process is normally followed by a multiplier. This scaling factor accounts for variations in the outcome of the actual semiconductor manufacturing steps, typically 1.0 for most technologies. The multiplier is a floating-point number from 0 through 100. So actaully its not L but a factor accounting for its variation.
Click to expand...


hey i'm just a beginner and i just post what i come across...
 

Re: PVT Conditions

A.Anand Srinivasan said:
onlymusic16 said:
Thats what i wanted to hear.

Process is normally followed by a multiplier. This scaling factor accounts for variations in the outcome of the actual semiconductor manufacturing steps, typically 1.0 for most technologies. The multiplier is a floating-point number from 0 through 100. So actaully its not L but a factor accounting for its variation.
Click to expand...


hey i'm just a beginner and i just post what i come across...
Click to expand...

It does not matter at all. We all are in learning mode and should not worry about how we are learning, the important thing is we are learning.:D Afterall, child is the father of man.:D
 

PVT Conditions

Process is for fast fast or fast slow ??
 

Re: PVT Conditions

Hi onlymusic16,

could you explain "Process is normally followed by a multiplier. This scaling factor accounts for variations in the outcome of the actual semiconductor manufacturing steps, typically 1.0 for most technologies" more clearly, for e.g asssume a case what will be the impact if the process is 2.0 .

Since process is directly related to fab, i would like to add one more question, we are considering Common path pessimissom (CPP) as well as On-chip variations on place and route flow, how is it related to or different from Process factor which you have explained earlier.

Regards
Nav
 

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