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actually you don't make a parasitic bjt. as the name implies it is parasitic. it is inherent from the cmos structure. if you have an nmos transistor, parasitic npn bjt would be, n for drain p for the substrate and another n for the drain.
to make a diode in cmos. connect the gate to the drain in either pmos or nmos. then you have a diode connected mos or a diode (as the name implies).
In standard p-sub CMOS process, you got two diodes.
One is N+/p-sub. You just draw a N+ region in layout. It form a diode between N+/p-sub. One thing to note: p-sub is always connected to ground.
Another one is NW/P+ diode. You can draw a NW first, then add a P+ inside NW region.
To accurate performance simulation, you must find help from your foundry.
Attached is the Picture of what exactly you are saying about , this might be the implementation in Standard cell architecture, where in, the area of diode layer is proportional to the current capability of diode , but when it comes to Analog/IO design mostly the MOS implementation of diode is formed by shorting drain and gate as one terminal and source and bulk shorted together acts as another terminal (This always ensure device operates in saturation region)
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