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How to delay the input by two clock cycles?

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manasiw2

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Hi.
I need to do following,
output should follw input after two system clock cycles.
Please suggest how to do it in VHDL.

thanks in advance.
 

The easy way is just add 2 register by serial and sample the output of last register.
 

    manasiw2

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hi

Just use double flopping nothing but two flip flops in serial, that output will be two clock cycles delayed with respect to input.
 

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