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designing pll for 100MHZ

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sridhara

sridhara

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100 mhz pll

my problem statement is to generate clock of 100 MHz using pll and the jitter must be minimum.... my tuning range of vco can be of our own choice .........problem .......i am not able to fix the other design constraints like

* phase margin
*charge pump gain
*charge pump current

help me in choosing (or finding)these values for very less jitter clock //...
or tell me some good links where can we get the design procedure....

how can we fix the gain of vco and phase detector....is it right that kvco and kpd cant be fixed and can be obtained only after design.....????

also tell me in what way does the phase margin determine the performance of pll
.....
 

vco pll 100mhz

try some basic/advance analog/PLL design books about the open loop and close loop stuff, and u'll get the idea
 

ωn ζ matlab

Let me put it this way
(1) Charge pump current =5uA
(2) Digital PFD
(3) Kvco around 100Mhz/V
(4) 2nd LPF, R around 50Kohm, C aound 400pf

This should give you sth around 100ps cycle-to-cycle jitter, in real silicon
 

    sridhara

    sridhara

    Points: 2
    Helpful Answer Positive Rating
pll all a hotmail .com

all of these must be done , using a system analysis of the PLL , u need to make the model , simulate and sweep all these paramters and choose the best which get ur spc's
there are alot of discussion here about PLL and also a lot of books

khouly
 

charge pump pll damping factor

hung_wai_ming(at)hotmail.com said:
Let me put it this way
(1) Charge pump current =5uA
(2) Digital PFD
(3) Kvco around 100Mhz/V
(4) 2nd LPF, R around 50Kohm, C aound 400pf

This should give you sth around 100ps cycle-to-cycle jitter, in real silicon
Click to expand...

can u please explain me how u arrived at this(i want the formulas and theory behind this..) ....i am exactly in need of this datas and if possible quote any links for the same.....
thanks in advance.....
 

pll to 100mhz

sridhara said:
my problem statement is to generate clock of 100 MHz using pll and the jitter must be minimum.... my tuning range of vco can be of our own choice .........problem .......i am not able to fix the other design constraints like

* phase margin
*charge pump gain
*charge pump current

help me in choosing (or finding)these values for very less jitter clock //...
or tell me some good links where can we get the design procedure....

how can we fix the gain of vco and phase detector....is it right that kvco and kpd cant be fixed and can be obtained only after design.....????

also tell me in what way does the phase margin determine the performance of pll
.....
Click to expand...


I suggest you to build a PLL matlab model to choose this parameter.
 

Hi all,
Dear hung_wai_ming@hotmail.com can you through more light on how to compute in general this parameter from where you starts and what parameters/factor to take in considerations.
Thanks in advance.
 

Time constant τ2 τ2 = R2C2
Time constant τ1 τ1 = R2*(C2*C1)/(C2+C2)
Crossover frequency ωC rad/s ωC = 1/sqrt(τ1τ2)
Natural frequency ωN rad/s ωN=sqrt((KCP*KVCO)/(N*C2))
Damping factor ζ ζ= (R1/2)*sqrt((KCP*KVCO*C2/N))
DC Loop gain K K=KCP*KVCO*R2/N
3-dB bandwidth ω-3dB ω-3dB = ω-3dB*sqrt(2*ζ2+1+sqrt(2ζ2+1)2+1))

Overload limit > 1; >10 is better L L=2*π*Fcomp/K
Phase margin Φ Φ = atan(2*ζ*sqrt(2*ζ2+sqrt(4*ζ4+1)))
Lock time TL μs TL = 2*π/ωN
Lock range ωL rad/s ωL = 4*π*ζ*ωN
 

    sridhara

    sridhara

    Points: 2
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Thanks a lot, could you please attach the shematic of the studied PLL.
Awsome thaks.
 

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