a trick question on pole calculation

please refer to attachment

Hello maninnet,
the problem with method 2 is you cannot assume N to be AC ground since if you assume it to be AC ground then you are assuming that there is no signal at that point but in fact you are trying to calculate the pole for the signal that you input to N! If truly N is AC ground then method 1 is wrong since then you won't have miller effect on C1.
Another thing to point out is that the resistance looking into the cascode current source is (ro+Rd)/(1+gm*ro) where Rd is the impedance at the drain, here you show a current source connected to the drain which would have infinite impedance resulting in the impedance you see at the source to be infinite too and not 1/gm2.

1. thanks for your ac ground explanation, which clears my concern, i am just so silly to neglect the fact that N

is where the signal comes in.


2. for the additional concern you pointed out, i can't agree with you, this is tricky. If you do the small signal
analysis, you will finally see that impedance looking into M is roughly 1/gm2 (of courese we assume ro1 and ro2 is
big enough compare to 1/gm2), the equation you write is not valid when Rd is infinite, it is actually r02/(1+gm2*ro2), or roughly 1/gm2. You could refer to Baker's "CMOS Circuit Design, Layout, and Simulation" (2nd ed)
p731-p732(equation 22.36 and small signal figure 22.28 ), equation 22.36 is esentially the one you write, but not valid for currence source load.

Hello Maninnet,
I cannot seem to derive what you explain in your second point and I don't have that book with me right now. So if you can maybe post the derivation maybe that would help me see your point. With my derivations I still think that if your drain is just small signal floating then the small signal impedance you see at the source should be infinite, thats what I get on solving the small signal model.

Added after 28 minutes:

I checked Baker's book, over there it doesn't mention that the equation 22.36 is invalid for a current source load. Also if you analyse it by saying what if I have a non ideal current souce which has a resistance Rd then the impedance is given by the equation I wrote so having an ideal current source with infinite impedance should simply be the limiting case of that equation i.e. then the impedance should be:

Limit (Rd -> ∞) (ro+Rd)/(1+(gm+gmb)ro), which would again tend to infinity.

deleted

In attachment 2 the assumption that D is at 0 potential is not correct since to 0 out a current source you need to open circuit it. By saying D=0 you ave saying that it is AC ground which is incorrect

This circuit has a pole at 1/(2 pi r1 c1) and a zero at gm1/(2 pi c1). Note that transistor 2 is disconnected from the circuit in small-signal analysis, and its parameters cannot appear in any solution. You cannot use Miller's theorem because the circuit gain is frequency dependent. You have to solve it by using KCL. To conclude: either of your solutions is wrong.

Had your teacher accepted any of them as a right solution?

jasmin_123 said:

You cannot use Miller's theorem because the circuit gain is frequency dependent.

Click to expand...

It is better to refer it as the Miller Approximation because the results it gives are not accurate in actual circuits since it always assumes there is no feedforward through the element we break. Over here it does give an approximate answer. We don't see the real effect for it because we assume the source connected to M1's gate has no source resistance. Once we add the source resistance then the pole at the gate is given quite nicely by the miller approximation although the gain is still dependant on the frequency. Best way to see it is to solve it using KVL, KCL and then see how the pole includes the miller multiplication factor.

to both jasmin_123 and aryajur:

1. The circuit I draw in attachment 1 is a telescopic amplifier cited from an exam (attachment 4), the output is taken between the drain of NMOS 2(attaachment 1) and the currence load that is supposed to be replaced by a cascode of PMOS pair. To address my originall silly concern (the ac ground question) that aryajur had already answer and to simplify the subject, i used a current source load and purposely set the souce impedance of the input side to 0, that is what you saw in attachemnt 1


2. To aryajur: I apologize that you are correct and I am wrong: the equation (ro+Rd)/(1+(gm+gmb)ro) you write could be confirmed in several classic analog ic textbooks regarding the input impedance of CG stage. it reduces to roughly 1/gm if ro is infinite or Rd is small compared to r0. For a long time, i just simply write the impedance looking into the source as 1/gm without carefully considering the loading connected to the drain, thanks for leading to me the review the basic stuff.


3. To jasmin_123: I admit that miller's method is only good for hand analysis, it does not reveal the zero location and also "the circuit gain is frequency dependent" , which will cause inaccurate result as explained in Baker's book. I use miller's method here becasue that is a common treatment in the exam (attachment 4).


4. Now to both of you: refer to attchment 4 (the exam question where the attachment 1 is based on (refer to question 2 part 2)) and attachment 5 ( from Baker's book 2nd edition, equation 21.84 and denominator in equation 21.86), they still write the input impedance as 1/gm, how to explain?

Hello Maninnet,
In the exam question that certainly is not the right answer assuming the PMOS cascode has impedance in the order of gm rop², the impedance looking up the source would be in the order of ro. Although the impedance looking up to the source of the cascode can be 1/gm even if there is a PMOS cascode load in 1 case. That is if your dominant pole is the output pole which is dominant because of a large load capacitance connected to the output. In that case when the source pole frequency comes in that case the output node is nearly like a AC ground and then the impedance looking up is then nearly 1/gm, I think thats that baker intended it to be, although I did not read it but from the figure he does show a Cload connected to the output.

Hi, maninnet,

Are you kidding? Which circuit are you talking about? You have already mentioned at least four different circuits. I also do not understand your difficulties: any small-signal circuit is linear and can easily be solved analytically. Regarding "no Miller effect" in attachment 4, it is not true.

Jasmine

Hi jasmin_123,

sorry to confuse you, the circuit i talked about is in attachement 5, figure 21.37 and 21.38, equation 21.84 and 21.86, baker still writes Rin=1/gm, i think the Cload in the schematic only comes to play in high frequency, at relatively low frequency, the Rin should be quite large rather than 1/gm

Hi, maninnet,

Baker considers a general AC case, without distinguishing between LF and HF, and, hence, all his capacitors, including Cload, are short circuited. Also the signs "equal exactly" in the equations suggest the same. What confuses is the "Big" value of a capacitor. One can think that all the other capacitors are not big enough to have a zero impedance.

I admire your desire to understand analog circuits and the way you do it, looking at them from different angles. What university are you from?

Jasmine

jasmin_123 said:

Hi, maninnet,

Baker considers a general AC case, without distinguishing between LF and HF, and, hence, all his capacitors, including Cload, are short circuited. Also the signs "equal exactly" in the equations suggest the same. What confuses is the "Big" value of a capacitor. One can think that all the other capacitors are not big enough to have a zero impedance.
Jasmine

Click to expand...

One of the most confused statements about AC analysis on this board...

Student exams coming up soon ?

n1cm0c said:

One of the most confused statements about AC analysis on this board...
Student exams coming up soon ?

Click to expand...

Could you please be more explicit?

jasmin_123's statement is actually correct, baker implicitly assume that the circuit is used in a appropriate frequency range that the Cload will override the impact of the cascode pmos pair, so that Rin=1/gm.

aryajur:

the problem with method 2 is you cannot assume N to be AC ground since if you assume it to be AC ground then you are assuming that there is no signal at that point but in fact you are trying to calculate the pole for the signal that you input to N! If truly N is AC ground then method 1 is wrong since then you won't have miller effect on C1.

Click to expand...

I just realize that your explanation on method 2 in my attachement 1 is incorrect.
The theory origin in method 2 is open-circuit time constant (Sedra's micorelectronic circuit 5th ed p575-576), that is actually the 1st hand analysis method i learn to find poles, but kinda forget it after getting exposured to miller's method so frequently.

You are right, although open circuit method does not identify any pole associated with any node(so we cannot say that using OC the pole at node M is this) it can just be used to approximately estimate the BW of a circuit and it is only reasonably accurate for dominant pole systems. One thing to keep in mind is when we try to estimate the poles of a system using Miller approximation, Open Circuit Time constant method, Short circuit Time constant method, we are already taking huge approximations and poles/BW estimations being factor of 2 off is still a good answer sometimes answers would be way off. The only way to get the accurate answers is to use SPICE, or if you just consider 1st order models is to solve the circuit fully using KVL-KCL.
In this particular case when you solve your circuit fully assuming that the current source has an impedance Rd (ro is much larger for both transistor) then you see the answer you get by Method 2 is correct. So why does Miller approximation fail? The explanation for that could be because Miller approximation works only if by breaking the path (through C) the gain upto the frequencies of interest does not change. So if C is 0 gain is 1 from input to cascode node but when C is there the gain is less than 1 at the frequencies where C starts interating with the Bandwidth. Also in the Miller approximation the Constant factor '1' is already a huge percentage of this error in the gain change, so the answer from that is much more pessimistic.

aryajar:

1. i defenitely agree on your point on the limitation of the two hand analysisi methods, the origin of this post is i can not identify the method or theory for method 2, but now it is clear.

2. You mentioned the "short circuit time constant" mehtod, which is kinda familiar to me, but can not remeber where it comes from, is it also from sedra's book?, please give me the reference.

3. i am confused that "So if C is 0 gain is 1 from input to cascode node", if the current source load replaced by a pratical Rd, the gain (if C is 0) from input node N to cascode node (the output node that i did not lable in attachment 1) is gm1*((gm2*ro2*ro1)//Rd), how come it is 1? or if you mean gain from N to M, it is still much bigger than 1, could you clarify?

By cascode node I meant Node N. Assuming ro for both transistors are infinite. In that case resistance looking up the source is 1/gm and then your gain becomes gm*1/gm = 1 upto node N.
You can read about open circuit time constants and short circuit time constants in CMOS RF IC Design by Thomas Lee, he gives a very nice explanation and more importantly he describes clearly the limitations and what capacitors in the circuit contribute in the analysis.