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dft question (pls answer )

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can any one tell me what are the different information does a designer give to dft person along with the netlist and library.
 

Also give the clock domains, reset strategy, latches, combinatorial loops if any
 

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    gold_2007

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They will give u clock and reset.. bcoz these are the most important thing u have to consider and u have to take care about the synchronism..
Muxes, clock ,reset are the most important thing for a dft designer to choose
 

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    gold_2007

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critical path, sta scripte
 

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    gold_2007

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Hi All,

Along with the above information they will also tells the power domain info and jtag register configurations that we need's to do for the required modes and controlls..
regards,
ramesh.
 

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    gold_2007

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rameshsuthapalli said:
Hi All,

Along with the above information they will also tells the power domain info and jtag register configurations that we need's to do for the required modes and controlls..
regards,
ramesh.
Click to expand...
Thanks ramesh and all
 

Dear Designer

my 2 cents in this discussion

1. Verilog netlist
2. STIL/TPF file (Standard Test Information file/Test Protocol file) , a procedure file generated from the DFT test compiler report
3. List of flip-flops in each scan-chain.
4. Scan input and scan output signals
5. Scan clock name
6. Signal to control the resets.
7. Scan mode/Test mode signals
8. Flops not part of chain and any reason.

Praise the Lord.

best regards,
www.vlsichipdesign.com
[Learn ASIC Chip Concepts both frontend and backend for free]
 

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    gold_2007

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