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Script to create Verilog top level module

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beowulf

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Hi all,
This might be the most comon problem/task for ASIC engineers. I need a script that will generate a top level module for 'n' verilog modules (in 'n' files)

Say I have A.v & B.v. The script should generate a ABTop.v such that

module ABTop(
clk
:
:
);

input clk;
input (etc etc)
:
:
output (etc etc)
:
:

A A_i (
.clk (clk)
:
:
:
);

B B_i (
.clk (clk)
:
:
:
);

endmodule

This can be a perl, tcl, shell script...Any pointers will be helpful

Thanks,
B
 

I think U shud read design file so that u get module name.. this name shud be used for instantiation !!

perl is easy for pattern matching. read all inputs n outputs from design file n u can creat TOP module file..
 

The logic is not an issue, I just wanted to know if somebody has done this already (its a common problem) so the wheel need not be reinvented.

btw, readers of this post can take a look at a tool called Topweaver (just google topweaver) which is a GUI based top level module creator. Pretty neat, but a script based tool will be nicer.

There was a site called tclforeda.com which supposedly had such tools, but the site doesnt exist anymore...

Thanks,
B
 

beowulf said:
There was a site called tclforeda.com which supposedly had such tools, but the site doesnt exist anymore...

Thanks,
B
Click to expand...

Try www.tclforeda.org

Also Emacs with AUTOINST can do what you are looking for.

Ajeetha, CVC
www.noveldv.com
 

    B

    beowulf

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