The timing in a latch based design

Hi ,
Can enyone explain me timing in a latch based design ??
How it differs from flip flop based design ??

thanks

Re: Latch based design

same doubt i am also having, can any body answer for this question , please help me.

Re: Latch based design

I am too searching for good material for latch based design and their timing.

Re: Latch based design

I heard about LSSD ( Level Sensitive Scan Design ) in DFT.. There we use latches for scan stitching.. I too want to know more about this, plz somebody post their comments.

Re: Latch based design

Hi kumar,

The latches you are mentioning are known as lock up latch,
When the scan from one clock domain is to be stiched to the scan chain for another clock domain then we insert lock up latch between two scan chains .....
scan input.....................scan chain for clock 1..........................lockup latch.........scan chain for clock 2........lockup latch................scan chain for clock 3....................scan output

Re: Latch based design

do you mean replacing all flip flops with latches,and replacing a single clock with
two non-overlaping clocks?This technology is not widely used now.

rakesh1234 said:

Hi ,
Can enyone explain me timing in a latch based design ??
How it differs from flip flop based design ??

thanks

Click to expand...

Latch based design

do you a ibm designer?

Re: Latch based design

Latch based designs are generally done to better the operating frequency. Say for example, few design houses use only Latches to design their processors. They try to get the maximum benefit out of the time borrowing concept, when using latches.

Re: Latch based design, possible with a standard flow?

Is it possible to do a latch-based design using a HDL language and a synthesis tool???? Or these designs are performed in gate-level abstraction only????

If you replace the flops by latches and use two non-overlaping clocks the design will be very compact, and due to time borrowing very fast as well. No to mention less power.

I remember that cadence BuidGates could perform time analysis for latch-based designs.

cheers

Latch based design

You can use synthesis tool to generate latches, but it has a very error-prone coding style.

Re: Latch based design, possible with a standard flow?

Arturi said:

Is it possible to do a latch-based design using a HDL language and a synthesis tool???? Or these designs are performed in gate-level abstraction only????

Yes, it is possible. The synthesis tool can infer latches based on the coding you have done.

Also wish to inform that any STA tool ( like Prime Time or the in-build STA engine in Magma ) can do a timing analysis for a Latch Based design. Again you can have a control on the borrowing by either using balanced borrowing technique or a relax borrowing technique. Both the technique are supported by the STA tools.

Click to expand...

Re: Latch based design

Latch base design is used for time borrowing design. In general, Latch is one kind of registers that store value like FFs, but different in sensitive with FFs.
Because Latch are level sensitive instead of edge triggered, the latch can borrow time from the next state to meet timing.

For more information, please contact me!
Nguyen Phuc Vinh :?:
vinh.camau@gmail.com\]

Latch based design

Can u explain more on this how latch can be used to borrow time from next stage to meet timing

Re: Latch based design

Hi sim_333 and all,

As you known, FFs are edge sensitive and Latch are level sensitive. for meet timing circuit, the arrival time of data path must be ready at the input of regsiters (Latch & FFs). that mean arrival time must be less than required time when an clock even (level-sensitive or edge sensitive) happen.

Please load figure into attachment for your knowledge about latch-base design!
In below figure, you can see that a circuit with latch B in the middle of 2 boundary flipflops A & B. Clock period for 2 FFs is 10ns (FF-clock), the driven clock of latch is inverted clock of FF-clock. The data path between FF-A and Latch-B is 7ns (path1) and data path delay between Latch-B and FF-c is 2ns (path2).
If Latch-B is a FF, the path1 data path is too late to be captured by clock-edge even at 5ns (1/2 period). However, because of level-sensitive of latch, the data can be captured when signal-level of latch is still high. => the current state is meet timing, and the next state is also meet timing base on above causing.

You can describe the below figure in another ways, but the latch-base design is very useful for long-path fixing.

Thanks and see you later!

Re: Latch based design

latch has problem in DFT. I am wondering if any one see a library cell with
scannable latch. Also, ATPG tool can't handler latch(excluding lockup latch)very well

Re: Latch based design

The latch-based designs I know are very compact high-performance and low-power microprocessors. They are designed in gate level abstraction. These processors use time borrowing to achieve high frequencies.

For manufacturing testing (i.e., DFT) some special test programs are created. The processor boots from external memory and writes checkpoints to its primary outputs. These IOs are saved to create the test patterns. So all that the tester has to do is feed the chip with instructions (input patterns) and check the if the primary outputs have expected values (i.e., the check-points).

In order to achieve coverage the test program must be written carefully.