What does .sdc file include?

can anyone elaborate this......

.sdc file:------it contains clk definition to all the paths in deisgn,false & multi cycle path, IO delays, max, min delays, source latency, case analysis........

anthin more files it has/??
wat is this case analysis??

wat is the diff bet timing exceptions & timing constraints??
i think timing exceptions r fals & multi cycle path....correct me if i'm wrong......

thanks in advance

case analysis sdc

sdc stands for "Synopsys Design Constraints",
An ASCII text file (with the extension .sdc) that contains design constraints and timing assignments in the industry-standard Synopsys Design Constraints format. The constraints in a Synopsys Design Constraints File are described using the Tcl tool command language and follow Tcl syntax rules.

.sdc file

SDC contains optimization and DRC constraints.

Generally, MCP,false paths, Max/Min delay settings are called exceptions to the design. The reason being is, it overrides the single cycle timing behaviour of the design. Exceptions are subset of constraints.

Constraints may consists of clock definitions,IO delays,max transitions,Load values to the design, case analysis, constant value settings, Dont use settings, ideal net , ideal networks ,max area and disable timing and many many more AND exceptions..

Case analysis is used to distingushed between the different modes you are using in the timing analysis. For ex, the timing analysis is carried for DFT mode/Functional mode/PLL mode/etc... set_case_analysis 0 TEST_MODE ,will be used to functional timing analysis(Ofcourse it depends on your RTL coding).

Finally, SDC doesnt contain clk defintion to the all the paths in the design. Depends on the mode of SDC, the clock definitions will be constrained. Means, in the design, some registers are not required to do the timing in specific mode. The clock defintion to that register is not required to keep in that SDC.

Regards,
sam

sdc file synposis

ideal network could be set in sdc, I don't think so.
which version it support?

SDC file

Okay, what constrains could not be included in the SDC file?

Thank you!

refer this

https://vlsi-expert.blogspot.in/2011/02/synopsys-design-constraints-sdc-basics.html