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yes... we prefer to use the nand implementation...
its because the nor gates can be slower compared to the nand gates...
in cmos tech the nor gate has two pmos in series making it slower
due to the poor mobility of the holes...
however the two pmos are in parallel in nand gate...
which doesn that much slow down the operation of nand gate....
yes we prefer sop implementation only because it requires nand gate. in the nand gate two pmos are in parallel while in the nor gate the two pmos are in series. so the latter case leads to delays because of the low mobility of the holes. and to match the speed of operation of pmos with the nmos the size of the pmos has to be increased. this requires more silicon area which again leads to more cost.
responding to ur question lordsathish; u should be familiar with device level operation.
For P-chanel effective carriers are holes; which represents an empty space in atom. An electron occubies this empty space leaving a hole, the same occurs for this empty hole.This results in an effective hole movement across semiconductor.
Finally, whick do u think is faster looking for an empty space to fill; in p cannel case;where electrons are a minority,or motion of electrons in case of an n-channel.
yes... we prefer to use the nand implementation...
its because the nor gates can be slower compared to the nand gates...
in cmos tech the nor gate has two pmos in series making it slower
due to the poor mobility of the holes...
however the two pmos are in parallel in nand gate...
which doesn that much slow down the operation of nand gate....
Whether the operation (slower r faster) does depend on inputs u give it to it????
The Diffusion constant for holes is always less than that of electrons..
(For diffusion constant definition , u can refer Electronic Devices by Millman, book)
I think this plays a role in having holes less mobility than Electrons...
The Diffusion constant for holes is always less than that of electrons..
(For diffusion constant definition , u can refer Electronic Devices by Millman, book)
I think this plays a role in having holes less mobility than Electrons...
The reason why Nand gate is considered is that the area of Nor is more than Nand, also its capacitance is more than Nand. More Capacitance therefore more Silicon required therefore more cost and NRE becomes more also it can cause TTM to be a bit longer.
Usually in some Designs designers sometime disable the Nor functions...
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