Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

What are the effects of these IO constraints?

Status
Not open for further replies.
D

designer_ec

Member level 4
Joined
Mar 31, 2007
Messages
68
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
1,752
Hi ,please explain each of fallowing topics elaborately.

set_input_delay
set_output_delay
set_drive and set_driving_cell
set_load
Please let me know the what are the effects of each,how these recognize in timing report,how these effect on timing and timing report.
 

set_input_delay explain

hav u refered doc on DC?
 

io constraints

The set_input_delay command specifies the amount of
delay from an edge of the CLK clock to the arrival of data on input
pins in1 through in4. It establishes a timing constraint at those
inputs and specifies the arrival time of data with respect to the
CLK clock.
The set_output_delay command specifies the amount of
delay from each output to the external device that captures the
output data. It establishes a timing constraint at the outputs and
specifies the required time for output data with respect to the CLK
clock.

Dinesh

Added after 50 seconds:

set_driving_cell command sets the
driving cell for these ports to the IV (inverter) library cell.

The set_load command sets the external
capacitive load to 1.0 unit for these ports.

Dinesh
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top