Verification: Your Suggestions Needed

Hi friends,

My company is going to start front end verification business. We are not sure which tool or which methodology should we go for!!!!!!!

which language?
System Verilog?? e?? vera?? SystemC??

which tool?
Questa AFV?? Specman?? Vera?? VCS??

What is the current trend in the market?? Please suggest verification tool and language which are good to meet the future requirements too.

Thanks

If you are already familiar with verilog, then system verilog may be your best choice.

xstal said:

Hi friends,

My company is going to start front end verification business. We are not sure which tool or which methodology should we go for!!!!!!!

which language?
System Verilog?? e?? vera?? SystemC??

which tool?
Questa AFV?? Specman?? Vera?? VCS??

What is the current trend in the market?? Please suggest verification tool and language which are good to meet the future requirements too.

Thanks

Click to expand...

It depends on several factors, perhaps too much to arrive at conclusion via email. Nevertheless, SystemVerilog is the way to go for near future. E//Vera is good if you want to target existing user base. Is your business model services based? If so you may need that know-how. Tell us more about the business model - is it services or for your own usage?

Methodology - today it depends on the tool you use, though the concepts in VMM are widely deployable in many/all.

We at CVC specialize in such flow recommendations for local customers in Bangalore, if you would like a more professional assistance, drop me an email ajeetha <> gmail.com. Look at our Products/Services page from www.noveldv.com for details.

Good Luck
Ajeetha, CVC
www.noveldv.com

go for VCS and adopt systemVerilog flow.
and ofcorse as ajeetha say,there are lot many factors to look upon but systemVerilog will be the language for verification in coming time. and VCS has an excellent supoort for that.


-Manmohan

IP or SoC business? Maybe Cadence Incisive Flow or Synopsys Discoverly Flow may help you.

Thanks to all.

Thanks Ajeetha.. I was actually expecting a reply from you for this topic. Yeah we will take help of professional services like you. Before that we want to do some ground work.

We will be having services based business model. Our managers are more inclined towards cadence Incisive because it supports "e" as well as "system verilog".

What do you think about Synopsys "Discovery Verification Platform" ? This gives support to open vera along with system verilog.

which one do you recommend if we adopt VMM.

Thanks,

xstal said:

Thanks to all.

We will be having services based business model. Our managers are more inclined towards cadence Incisive because it supports "e" as well as "system verilog".

Click to expand...

But be careful about their SV maturity, see cdnusers.org for recent updates, their SV is still in the making, but seeing a good progress.

What do you think about Synopsys "Discovery Verification Platform" ? This gives support to open vera along with system verilog.

Click to expand...

With VCS (Synopsys Discovery stuff), things are lot stable as they have been doing this for the past 3 years or so. Sure there are some unimplemented stuff, occassional crashes etc. but they have a solid/robust methodology to go with SV and that shows their maturity indeed.

which one do you recommend if we adopt VMM.

Thanks,

Click to expand...

Well for VMM to work you need lot of good SV support, I see that ncsim doesn't yet fully have things like mailbox, virtual inetrface, program etc. in great shape, so with VMM you are far better off with VCS-Questa-NC in that order of preference

In anycase since you mentioned a services model, I would recommend you learn SV the right way with VMM + VCS, then adapt it to Questa and NC as well. That's what we do at CVC as our potential customers may use any of the 3 tools.

Good Luck
Ajeetha, CVC
www.noveldv.com

aji_vlsi said:

But be careful about their SV maturity, see cdnusers.org for recent updates, their SV is still in the making, but seeing a good progress.

Click to expand...

You mean to say if we are thinking about SV, Cadence is not the wise option!!
Well how do you rate Cadence present SV support out of ten. How good is Questa AFV??

VCS is winning the race it seems. I am not sure if synopsys is an option for our managers. Thanks for giving the order of preference for the tools.

You said learn Sv the right way. What is the right way of learning SV???

Thanks

xstal said:

aji_vlsi said:

But be careful about their SV maturity, see cdnusers.org for recent updates, their SV is still in the making, but seeing a good progress.

Click to expand...

You mean to say if we are thinking about SV, Cadence is not the wise option!!
Well how do you rate Cadence present SV support out of ten. How good is Questa AFV??

Click to expand...

Clearly Questa is ahead, however they have no testbench background. CDN has Verisity - means 10+ years of testbench experience, so their understanding of what it takes to do constraint solving, coverage, assertions etc. is much more than Mentor. So language wise Questa is surely ahead, and even sometimes ahead of VCS I heard (parameterized class for example).

VCS is winning the race it seems. I am not sure if synopsys is an option for our managers. Thanks for giving the order of preference for the tools.

Click to expand...

Again that is not just b'cos of language alone - the whole game of constraints, coverage etc.

You said learn Sv the right way. What is the right way of learning SV???

Thanks

Click to expand...

Depends on what you want to do with it - design, assertions or testbench? For TB - a good methodology is needed to get maximum out of this vast language. Design is almost quite easy to pick up. Assertions - maybe 1 or 1.5 day training and also a followup usage with Formal tools.

As you perhaps know already, my company provides all these variants of trainings in Bangalore

Regards
Ajeetha, CVC
www.noveldv.com

xstal said:

Hi friends,

My company is going to start front end verification business. We are not sure which tool or which methodology should we go for!!!!!!!

which language?
System Verilog?? e?? vera?? SystemC??

which tool?
Questa AFV?? Specman?? Vera?? VCS??

What is the current trend in the market?? Please suggest verification tool and language which are good to meet the future requirements too.

Thanks

Click to expand...

Hi ,

I think the HVL is not very important in verification. You must setup a good verification flow for your project. You can refer to VMM provided by synopsys.

Thanks.

Thanks for you replies....

Ajeetha could you please let me know where can I purchase the low cost indian edition of the following books
**broken link removed**
One of the book is authored by you.

Thanks,

xstal said:

Thanks for you replies....

Ajeetha could you please let me know where can I purchase the low cost indian edition of the following books
h**p://www.vmm-sv.org/resources/resources.html
One of the book is authored by you.

Thanks,

Click to expand...

As of now there is only US edition, I do have few copies in Bangalore for faster shipment to India customers. Also one can choose to make payment in INR if needed.

We at CVC are finalizing a "cookbook" style guide that will help you build a VMM TB from a conventional task based TB, this will be part of our VMM trainings.

Drop me an email at ajeetha <> gmail.com for details.

HTH
Ajeetha, CVC
www.noveldv.com