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A question on the standard ESD test

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chang830

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Hi,
We know, in the stardard HBM ESD test, three chips will go through the ESD ZAP with same mode. If all the three chips passed the ESD ZAP, then we think the chips passed under this mode.
But for my chips, I found an interesting thing. In the three ESD ZAPs, one chip passed 2000V in HBM mode, one failed in 2000V, the 3rd one even did not pass 1000V. If there is a weak path in the chip, it should fail at about the same level. Then why it have so much descranpancy?

Would anyone pls. give me some hints?

Thanks
 

First, your circuit is marginal.
Second, your chip can be from different locations in the wafer, so results can be variable.
Third, and most important, pls double check with IO has passed and which IO has failed. I think the passed IO location MAY be different from failed IO location.
My experience is:
One chip with say P10 passed at 2000K can be failed at another chip, by less than 500V difference in typical HBM test.

Also, it may due to your circuit marginality. Do more testing on more samples to get more meaningful statistics before you draw conclusions. Usually, I do more than 10 samples before I can draw conclusions on any happening.
 

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    chang830

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