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Dummy Gate DRC errors with SCMOS rules through MOSIS

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nikremt

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I want to use dummy gates for better MOS transistor matching, however, I am using the SCMOS_SUB3ME rules from MOSIS. Whenever I layout a dummy gate as suggested in "The Art of Analog Layout" by Alan Hastings, I get DRC errors. I violate rules 3.3 and 3.4 (**broken link removed**)

Has anyone out there delt with this before? I believe that somebody has bound to run into this problem before using the rules from MOSIS. Does anybody know any kind of solution for this? Do I have to disable the DRC in the dummy gate region? I really don't want to have to disable it.

Also, one more question... To be a dummy gate, does the Poly need to overlap that active region?

Thanks in Advance,

Tim
 

you can also create dummy transistor using shorted transistor. just do the ordinary layout for transistor and shorts it's drain and source together. i think it can act as dummy. i see this method on some lecture note that i've forgot the source. using this you will not violate the scmos rule from mosis.
 

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    nikremt

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I found these notes on Analog layout. In these notes they state that you should use dummy transistors but they don't show an example. If anybody has a picture of how to do this ( I am pretty sure I am doing it right, I just want some confidence before I fabricate), it would be really helpful for me and others in the future.

Apparently, the *.pdf file has already been attached to a thread here:
 

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