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Simple combinational circuit question..

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ahmad_abdulghany

ahmad_abdulghany

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Hi,
I want to make the VHDL code for a simple block that simply map every di-bit input to four-bit output, as follows:

00 >>> 01 01
01 >>> 01 11
11 >>> 11 11
10 >>> 11 01​

I did it concurrently in this block architecture simply as follows:

out_s(0) <= '1';
out_s(2) <= '1';
out_s(1) <= in_s(0);
out_s(3) <= in_s(1);​

Will this be done every clock edge of that block clock?? Notice that i didn't put it inside process..

Do you have comments on the method as well as the code?

Also I have a little question here, how will this code be synthesized on the FPGA?

Thanks in advance,
Ahmad,
 

Your code is done in continous fashion, there are no clock. All architecture body is theated as "main" process. In the simulation it is computed at every simulation step. In the FPGA circuit it will be simple combinatorial function, with out any registers/clock.
It can be written in more elegant form (for better clarity and any changes in the future):

Code: 
with in_s(1 downto 0)  select
            out_s(3 downto 0) <= 
                 "0101" when "00",
	              "0111" when "01",
	              "1101" when "10",
	              "1111" when "11"; -- or when others;

How it is synthetized? It depends from FPGA internals and synthesis options. It can be 4xLUT (even 2xLUT) with 2 inputs, or small 4 bit memory with two bit address lines or... even it can be done on some spare resources inside CLB's of your FPGA if your synthetizer is smart. For exactly this data the good synthetizer will find that two of the output signals are constant and for the rest it is simple copy of the inputs. It looks that there are no real resources inside FPGA will be used, only interconnections.
bis
 
bis_ said:
Your code is done in continous fashion, there are no clock. All architecture body is theated as "main" process. In the simulation it is computed at every simulation step. In the FPGA circuit it will be simple combinatorial function, with out any registers/clock.
It can be written in more elegant form (for better clarity and any changes in the future):

Code: 
with in_s(1 downto 0)  select
            out_s(3 downto 0) <= 
                 "0101" when "00",
	              "0111" when "01",
	              "1101" when "10",
	              "1111" when "11"; -- or when others;

How it is synthetized? It depends from FPGA internals and synthesis options. It can be 4xLUT (even 2xLUT) with 2 inputs, or small 4 bit memory with two bit address lines or... even it can be done on some spare resources inside CLB's of your FPGA if your synthetizer is smart. For exactly this data the good synthetizer will find that two of the output signals are constant and for the rest it is simple copy of the inputs. It looks that there are no real resources inside FPGA will be used, only interconnections.
bis
Click to expand...

For your code, Should i put it inside a process?

For my code, i still don't know what's wrong in mine? Is there something bad in it?

Thanks,
Ahmad,
 

This code can be placed anywhere between begin and end of the architecture body. Or inside this architecture you can write some proces and insert this code between begin and end of that process. In some of the simulators it can be better if you add in_s signal on the process sensitivity list, for the real synthetized device it das no matter. Placing that code (combinatorial logic) "directly in the architecture body" or "inside proces inside architecture body" is only matter of the codding style.
For my code, i still don't know what's wrong in mine? Is there something bad in it?
Click to expand...
Your code is OK, there are nothig wrong. I have place my example how it can be written in a form which will be more readable and undersandable in the future (if you need make some code inspections/changes after one year the work will be easier in my opinion).

bis
 
Salam Ahmad,

you can make it with a "with select" between the begin and end of the architecture
or also in a "case" or in an "if else" in a process ( with all the block inputs in the sensitivity list to assure that it's combinatorial )

if u need it only with clock then put it inside a sequential process and the clock in the sensitivity list, but i guess u want it a simple combinatorial part, right?


Salma :)
 
architecture ---------


signal sel:std_logic_vector(1 downto 0);
-----
-----

begin

process(sel,---)
begin
case sel is
when "00" => out_s<="0101";

when "01" => out_s<="0111";

when "10" => out_s<="1111";

when "11" => out_s<="1101";

when others=>
null; -- or out_s<="0000";

end case;
end process ;

end beh;

Added after 1 minutes:

This will generate four 4X1 mux.
 
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