What are interview questions based on CMOS IC layout?

what are interveiw question based on cmos ic layout ?

Re: interveiw question

Mos structure?
The tools you have used including DRC,LVS,LPE,etc.
How to improve matching,etc.
....

interveiw question

What techniques can be used to negate process related asymmetries? (e.g. common centroid layout)

interveiw question

floorplan and so on

interveiw question

match ,esd and so on

interveiw question

When u ask this question, it means you're a begineer. As a begineer, basically, ppl will ask you some of the questions below. (I was being interviewed long time ago as a IC layout designer)
(1) CMOS technology process fabrication. Maybe BIPOLAR depending on your company
(2) Device matching, either transistor, resistor or capacitor
(3) Device characteristics across temperature, like what's the sign for n+ resistor, p+ resistor.. sth like that
(4) Unix programming knowledge as most of the layout work now is an automatic job written by scripts

Above are basic layout questions. If you can tackle well the above four topics, I am sure you can have good chance.

As an intermediate engineer, you need some more
(1) Floorplanning skills, meaning how you partition the analog blocks wisely and whole chip wisely. It's big topic.
(2) Effects that affect device performance, like antenna effect, EMI, EMC, device mismatch, IR drop, Crosstalk, Signal integrity.. Again, big topic
(3) Project tape-out experience and your flow. We talk about REAL flow, instead of flow from university. University flow tends to be much simpler than flows in company. Don't just say DRC/LVS pass and you are done.. No.. you are dead..

interveiw question

what are interveiw question based on cmos ic layout ?
-- Are you familiar with CMOS IC Layout Design like , what are the tools have you used ,

It could be from asking your to draw few cell layouts to a bigger examples

Best is you refer to Alan Hastings

verification of the drawn Layout ( DRC/ERC/LVS)