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CMOS driver to drive large capacitanc load

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drabos

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Anybody knoes any article, book, chapter about CMOS driver circuits to drive large capacitance loads.
bootstrapped inverters or anything else

Thanks?
 

There is an op amp that is suitable for driving capacitive load, such topology can be seen in chapter 7 (GA-CF Configuration) operational amplifier of the book " Operational Amplifier, Theory and Design" by Johan Huijsing.

Option to is to used a tapered buffer topology
 

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    drabos

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I want to drive the gate of a very big switching MOSFET.
 

some single stage will be good as it will be load compensated
 

drabos said:
I want to drive the gate of a very big switching MOSFET.
Click to expand...
a bit off topic. however i'm interested to know how you determine the value of gate capacitance? from simulation or calculation? can you teach me how you do that. As far as i concern, in order to design let say an opamp, we need to know the value of load capacitance. In your case, i believe the gate capacitance is the load capacitance.
 

u can Do an AC analysis to calculate the cap.
 

yeah, the gate capacitance is the cap, I usually use operating point analysis to determine the gate capacitance, not an AC.
 

If you are using a monolithic power mos transistor you can estimate the gate capacitance by using the formula=WLCox.
 

Set up a chain of inverters (with an even total number, of course) such that each inverter drives ~4 times the capacitance that its own input node is. So start with the load, and size the inverter next to it such that its input node gate cap = capacitance of output node + diffusion capacitance of the inverter; repeat this procedure until you get to minimum size inverter. This procedure will get you very close to the minimum achievable delay for driving the large load.
 

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    drabos

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a chain of inverters is a good way to solve the problem of drive big loads, but you must see that every inverter has to have a multiplicity value, i.e. the first stage can be 1 inverter, the second one 3, 7, 21, etc... and the number of stages depends of CL (load capacitance)
 

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    drabos

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And what about bootstrapped circuits?
Does anybody have idea how to size the transistors in a bootstrap circuit?
 

drabos said:
yeah, the gate capacitance is the cap, I usually use operating point analysis to determine the gate capacitance, not an AC.
Click to expand...

you mean, you do operating point analysis and print the value of Cgs? this will represent the load capacitance? how big is your Cgs value? at what value we say that the Cgs value is big?
 

i use the cgg, rather than cgs. approximately. 10 pF.
What is the big? It is depends on the application, if you need high speed or very fast rise time, I think 500 fF can be high. But if you don't need so much speed, may be 1 pF still small.

Added after 4 minutes:

bootstrapped circuit: using capacitor to make the inverter faster.
many IEEE article about it, but not the sizing method and my problem is that I've tried some circuit but the performance not so good, may be I've szed the transistors in wrong way.:-(
 

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