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Low Dropout (LDO) Regulator Design

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moisiad

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ldo regulator design

Hi
I want to design an LDO with the following specifications (with either MOS or bipolar):
Vdd=3V
Dropout voltage =70mV
Output Current=40uA
PSRR=-80db@10MHz , -35dB@10GHz

Do you think it is hard to satisfy the above mentioned specifications? Do you have to propose any related document.

Thanks
 

analog ic design with low-dropout regulators

i don't know but are u sure about the -80 @ 10 MHz seems too much
 

low dropout regulator design

Yes, unfortunatelly the specs are the above mentioned !!
 

very low dropout ldo current constant regulator

Output Current=40uA ?
PSRR=-80db(at)10MHz is very difficult to design.
I think you should check if there's the similar product in the world. maybe you build it with that product.
 

low drop out

Hi renwl.
There is a mistake in the Output Current value which is 40mA (not 40uA).
Thanks
 

analog ic design with low dropout regulators

Psrr is too high for normal understanding.

Just think about it: your 0db gain bandwidth will be extremely large and seems that no human can do it.

are you sure about the spec?

I did a lot of projects about LDO, your spec is too....
 

ldo regulator spec

-80dB at 10MHz is kind of high. unless,

a) a very high gain-bandwidth amplifier
b) a very large output impendance
 

simple ldo regulator

Can you please inform me how the 0dB gain bandwidth is related with the PSRR specifications that i have.

Thanks
 

ldo frequency response in dropout

the higher the bandwidth, the more high frequency noise (i.e., supply noise) the amplifier can reject.
 

regulator design

szekit said:
the higher the bandwidth, the more high frequency noise (i.e., supply noise) the amplifier can reject.
Click to expand...
Can you explain it for me? Thanks.
 

high supply regulator design

the loop stops working after the gain BW, so u only reject supply at this region for rejection above that region u mainly depend on the decoupling cap at the output node to roll-off
 

low drop out high bandwidth

So that means that i need an amplifier with a bandwidth up to 10MHz. Am i correct?
 

pre regulator

no , u need a very large BW , as at unity gain the PSR will be 0, so to get -80dB u need some very large GBW , or u need a huge cap. to make the pole roll-off very quickly to get -80dB at 10MHz
 

low esr ldo

unless a very very large cap connect to the output,when the load res is very large..........
 

ldo regulator design

I have created a simple LDO (the classicall topology with a PMOS as the pass device), using a behavioral model of the OPAMP.
In any case it seems that the AC and the PSRR response is not affected significantly by the bandwidth of the OPAMP. It is the size of the pass device and the output capacitor that defines the AC and PSRR shape, since they set the two major poles of the system.
From the simulations it seems that is very hard to avoid the PSRR deterioration in the mid frequency range (1-10MHz), or even to move that deterioration in higher frequencies.

Please correct me if i am making any mistake. If i am correct, then what is the effect of the OPAMP bandwidht in the overall LDO performance, beacause i see not significant impact.

Thanks
 

ldo low esr

The Op-Amp governs the settling of LDO, and the transient response during loading is changed in real life. i agree the output cap (with ESR) and PMOS mainly controls the AC response and PSRR.
 

    M

    moisiad

    Points: 2
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pre regulator ldo high psrr

moisiad,

you catch the right point!

High frequency PSRR is by the cap ratio cgd(PMOS)/cout nothing else

The bandwidth and the DC gain of the regulator define how the transition region is looking. Typical you try to make the Q low so that the peaking in the frequency transition region has low dB.

From the dimensioning cgd direct depend on Imax and Vdsat of the PMOS
 

low drop out regulator

PSRR -80dB@10MHz? Good luck. State of art technology, 40dB @1MHz is very reasonable one.
 

low drop 431

There is no bibiographic reference about this topic ?

I think there is, so I don't know why are you discusing about if it is too much to achieve or whatever, just look at the references, simulate and then, conclude.
 

I recognize -80dB @ 10MHz will be tough to get but... what about this foolish idea.

Implement a pre-regulator with an ultr-low-offset OpAmp, whose GBW must be maximized. Use big capacitors on the reference voltage teminal as wel as on the pre-reg output. Connect a 2-pole passive filter from the pre-reg output to the Vin of the main regulator. Set the poles as to get at least -40 to -60 dBs of rejection @ 10MHz. You must use very low ESR capacitors and/or inductors.

Then you loop amplifier should have a GBW of at least 1GHz so to have a gain of the remaining 40dB at 10MHz.

in any case, I think a fully integrated solution is impossible.

I think the the drop out required is not compatible with the PSRR spec.

May the force be with you;-)
 

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