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Metal on Poly or diffusion

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gafsos

gafsos

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metal1 over poly mos vt

Hi,

a simple question: Why it's not allowed to route with Metal1 for exeple on poly or diffsion (NP/PP)

THX
 

metal over poly mos vt

Metal 1 is the immediate layer after the poly and if metal 1 carries a huge current there may be a chance of inducing electrons on the active poly which will alter the characteristics of that device........................
 

    gafsos

    gafsos

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Hi,

I talk about this situation ....

Plz I need ur advise

gsfsos
 

I don't know the reason for avoiding Metal1 over poly other than what jagadessh said.

However, for the diffusion case, the Metal line might act as a gate and create a parasitic channel. This becomes an issue if this parasitic channel connects two diffusions of opposite polarity.

Example: the p-substrate between two N-wells, this is why the separation between two N-wells has to be large if the N-wells are held at different potentials.
 

    gafsos

    gafsos

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Tnanks to all,

DRC check pass in this case, causa Met1 and poly are not in the same level, I want to know why it's not recommanded to root Met1 on poly... ?

Another sugesstions ??

TNX

gafsos
 

The above reasons are correct. Metal over poly carrying high currents might capacitively couple charge into a gate and affect the behaviour of a device. Also, Metal and poly can create parasitic devices when routed over wells.

One other reason not to route metal over poly on MOS transistors is that during etching of the metal, charged particles and residuals could remain on the dielectric near the remaining metal line. These charged residuals can unexpectedly change the behaviour, especially Vth, of a MOS transistor.
 

    gafsos

    gafsos

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I have one of this question too, if we want to reduce the resistance of the poly, can we connect it to the M1 with vias directly, that means the M1 will be routed directly above the poly for gate.
 

    gafsos

    gafsos

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What is your application? Principly, it should be avoided to route with metal over the active area of a MOS transistor period. If you have a very large transistor, common practice would be to use larger numbers of contacts or even a ring of contacts on the outer perimeter (not on the active area) of the transistor to ensure symmetrical gate connection.
 

    gafsos

    gafsos

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There is a practice where metal1 will be palced parellel to the gate inorder to reduce the resistance of the gate. Make sure that different signal line should not be routed over active poly region.
 

    gafsos

    gafsos

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Gate is a small part in the layout compared to adjacent elements,

And it's very sensitive, so it's not recommended in general to route any tracks that carry signals close to it..

Even its contact, it's put at the outer part of it to care for that ...

Cheers,

-- Knack,
 

    gafsos

    gafsos

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CK815 said:
The above reasons are correct. Metal over poly carrying high currents might capacitively couple charge into a gate and affect the behaviour of a device. Also, Metal and poly can create parasitic devices when routed over wells.

One other reason not to route metal over poly on MOS transistors is that during etching of the metal, charged particles and residuals could remain on the dielectric near the remaining metal line. These charged residuals can unexpectedly change the behaviour, especially Vth, of a MOS transistor.
Click to expand...

This is the right explanation ... for sensitive analog !
This rule is only valid for sensitive analog or RF !
In digital blocks, you don't really care if you Vth are precise or match another Vth :D
So, ... everyone use metal1 over gates in digital layouts.
So ... it cannot be checked in DRC.
 

    gafsos

    gafsos

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okguy, you are absolutely correct. I was inprecise in my reply. Of course you can route with any available metal over digital gates/transistors. I was just thinking analog.
 

    gafsos

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thx all for the execellent explainations above!!!
 

    gafsos

    gafsos

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So far, I learned so much from yours comments! Thank you!

Maybe we can think it on reliablity, you know, the Gate is very very important to cmos life, here, the life, I talked about, is mainly the parameter(i-v curve), if the parameter is varied so much with the original one, we think it's dead.
So, if the metal layer was very close to poly, the gate was affected very much, part reason is in fabrication, the other is in using. So the life would be decreased too much, I think!

It's a great thread! Thanks!

Cheers,
Alex
 

    gafsos

    gafsos

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thanks guys
i am new in vlsi field
the information mentioned above are very usefull for me
thanks
regards
analayout
 

    gafsos

    gafsos

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It is a priciple to avoid cross between metal and poly, but you can never achieve it successfully. Even for RF CMOS, it is allowed metal corss poly. The following picture is a real device in 0.18 RF CMOS process, which is a RF NMOS provied by foundry.

FYI.
 

    gafsos

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Hi all

I do hav a question. If in the layout, i have to connect the gates of 2 mos caps through metal1 and route it on top of poly of a pfet to make a connection elsewhere, i believe that is not an issue as it is not a current path. Please comment.

Regards
Brittoo
 

    gafsos

    gafsos

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the possible issue here is not the presence of current, since it's a gate terminal, but the role of the other pmos. if it is sensitive to Vt shifts, never ever do it. if it is justa bias transistor or powerdown transistor or any type of switch, you can do it. no issues.

hope it's clear
 

    gafsos

    gafsos

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I think for the case of metal on duffsion such as m1 over psub between two nwell(held at diffirent potential or not),the parastic channel won't happen at all,because there is channel stop implant under FO,it needs more than VDD to create a channel under FO if u check the PCM data carefully(8v for a .6 mm 5v cmos process).So dont worry about it.

Correct me if I make mistake ;)
 

    gafsos

    gafsos

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hi!

the way i look at it, you do not route over gates because of the thin oxide present below it. it is unlike the active region where thick field oxides exist. sure you are allowed to route over gates, but too heavy a metal can break your gate. especially for enhancement type transistors. there is practically only channel and a thin oxide to support the metals above it (if indeed you route over the gate).

- al
 

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