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Verilog Testbench for a VHDL entity

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yasser_shoukry said:
How can i write a test bench code using Verilog for a VHDL design ?

Thanks in advance
Click to expand...

The same way you would for a Verilog DUT. i.e.

Code: 
module vlog_tb;
  reg clk = 0;

  vhdl_dut dut_0 (.clk(clk));
endmodule

The point is, it is upto the tools to "bind" the DUT (or any module/entity/instance) to either VHDL/Verilog/SystemC etc. Sure languages have configuration constructs etc. But that's for single language domains usually. For e.g. the above trivial design can be simulated in VCSMX & MTI as follows:

Code: 
  vhdlan -work vhdl_lib vhdl_dut.vhdl
  vlogan -work vlog_lib vlog_tb.v
  vcs -debug vlog_tb -R -l run.log

And with MTI:

Code: 
  vcom -work vhdl_lib vhdl_dut.vhdl
  vlog -work vlog_lib vlog_tb.v
  vsim vlog_tb -l run.log

(NC has ncvhdl, ncvlog, ncelab, ncsim commands for the same).

Let me know if you need more specifc help.

HTH
Ajeetha, CVC
www.noveldv.com
 
Thanks a lot aji_vlsi, but what about ISE8.1 and ModelSim6.2 ? Does they need also some additional codes to get them work?

Thanks in advance
 

yasser_shoukry said:
Thanks a lot aji_vlsi, but what about ISE8.1 and ModelSim6.2 ? Does they need also some additional codes to get them work?

Thanks in advance
Click to expand...

ISE - no idea, if it is a simulator, read in their doc if they support Mixed language sim. Modelsim - yes, I have given all the command, what else do you need? BTW, ModelsimXE free version doesn't support Mixed language sim.

Ajeetha, CVC
www.noveldv.com
 

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