Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

What is the need for doing static timing analysis(STA) in ASIC design flow?

Status
Not open for further replies.
S

sivarajesh

Newbie level 1
Joined
Nov 28, 2006
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,292
can anybody explain what is the need for doing static timing analysis(STA) at beofre floorplanning and after floor planning in the ASIC design flow?
 

ASIC STA

We have to do STA before and after floorplanning for Checking any timing violation.

When u do prelayout STA, u have to check for any timing violation in the Synthesis Netlist. this is to check the quality of the Synthesis netlist.

When u do STA after floorplanning, we have to ensure that the floorplanning doesnt change any timing of the netlist.
 
Re: ASIC STA

Before floorplan,
1) check if the timing constraints are reasonable, and
2) check the quality of netlist with estimated wire-load.
----------------------------------------------------------------------------------

After floorplan,
--> check the quality of floorplan (the timing of placed netlist with net parasitics.)
-----------------------------------------------------------------------------------
 

Re: ASIC STA

there may be problem with the netlist itself,so zero RC check is must before floorplanning
 

ASIC STA

sorry, I do not find the pdf
 

ASIC STA

What tool ur using???
If its PT....the they have explained clearly in user guide.

for PT user guide......search in edaboard.
 

Re: ASIC STA

au_sun said:
We have to do STA before and after floorplanning for Checking any timing violation.

When u do prelayout STA, u have to check for any timing violation in the Synthesis Netlist. this is to check the quality of the Synthesis netlist.

When u do STA after floorplanning, we have to ensure that the floorplanning doesnt change any timing of the netlist.
Click to expand...

What are the critical points in prelayout STA??? or challenges???
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top