min or max ch Length in Analog RF...?

smaller cmos gate length higher the bandwidth

hi
in Analog RF which is better Using the min Ch length of the MOSFET Device or the maximum allowable Channel Length L?

if the answer is the max length ...this degrade the circuit Bandwidth...! ??

any related answer are welcomed
thanx

rds analog rf

you should simulate the ft of MOSFEF with the different length, then decide which one you want.

max.ch

An advice here is...

Increase channel length = Increase Rds (drain-source resistance). For lower bandwidth but better linearity.
Decrease channel length = Decrease Rds. For higher bandwidth, but poor linearity.

You need to check against the transconductance gm you need to achieve.

In turn, this gm will affect operating point of your amplifier, in turn the efficiency and operating bandwidth.

Hint: For short and narrow channel cmos processes, linearity is poor due to physical or mechanical imperfections. For digital VLSI , this is OK. Not the case for analog IC design.

ch.lenght

specifically i do a mixer on 0.13um tech on 2.45GHz
i noticed the linearity degrades with increasing ch Length but the process variations are very much with the min dimension MOSFET ...!

standard length of analog mosfets

(1) Process variation can affect everything from poly-Si interconnect (a problem getting more significant with deep sub-micron) to gate length. Not just minimum gate length MOS.
In fact, it is a very important factor for mixed RF-analog-digital IC design.
This is because RC increases with deeper sub poly-Si (due to smaller cross-sectional area), despite vertical traces are used to reduce this effect. RC of poly-Si affects the S-parameters!

(2) You need to check the transistor model used for your RF circuit simulation. You should be able to check it in your designer's manual, say if you are using Cadence SpectreRF or HP-ADS. Usually HSpice models.
Some design houses use their own models compatible to foundries.
For example, some foundries even provide Cadence compatible transistor models for different substrates, process tolerance, etc.

You also need to check the substrate you use. There are several substrates used for RF that confines the models you will use to accurately predict the performance and LO leakage (a problem always with Mixer design).

It is strange to see linearity decreases with increasing Rds (for wider gate length found in older cmos processes such as 0.25 and 0.35, which produce better RF-analog circuits than today's 0.18 and 0.13)

I have been using UMC, if not TSMC or SMIC. They have very good models and support.
If you are using CSM, I don't think they are good. They don't provide system and circuit design level support.

RF_babe said:

specifically i do a mixer on 0.13um tech on 2.45GHz
i noticed the linearity degrades with increasing ch Length but the process variations are very much with the min dimension MOSFET ...!

Click to expand...

is it just a typo or does the linearity of the mixer really degrade with increasing gate length? normally, if the gate length is increased, the gain degrades and you get better linearity. choosing the right gate length depends on the type and the part of the circuit, you design and the design requirements you have to fulfil. as an example, you may select a slightly larger gate length at your LO switch to supress flicker noise.

hope this helps.

minimun length have large ft but poor linearity.

there is trade-off between gain and transit frequency with respect to channel length. large L give higher gain while for higher frequency L min is suitable.