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Question about oscillator

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hktk

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I'm designing a oscillator this days, but I do not know how to make the output frequency stable under diffrent libraries, such as SS, FF and TT. Its structure is very common: using mirrored current from reference to charge and discharge a PIP capacitor. The mirrored current will be diffrent under SS, FF and TT, and the value of capacitor will change too. As a result, the output frequency will change from 70k to 160k, it's a serious problem. I know trimming the current or the capacitor will make sense, but I see no trimming on the layout of many chips. How can they make the frenquency stable? Is there any method to solve the problem without trimming?
 

In fact , the frequency changes withe the temperaure too .
So , is there any compensation for process and temperature in the circuits ?
 

Trimming or off-chip capacitor is needed to ensure oscillation frequency relatively stable.

It is still reasonable to design a charge/discharge current that track the PIP capacitor variations over temperature, so that to have same osillation freq. However, to design a current that track the process variation of PIP cap, is basically impossible.

There are some designs using MOS cap to replace PIP cap, MOS cap provide less process variation compare to PIP cap for some process, as they have better control at gate oxide.
 

hktk said:
I'm designing a oscillator this days, but I do not know how to make the output frequency stable under diffrent libraries, such as SS, FF and TT. Its structure is very common: using mirrored current from reference to charge and discharge a PIP capacitor. The mirrored current will be diffrent under SS, FF and TT, and the value of capacitor will change too. As a result, the output frequency will change from 70k to 160k, it's a serious problem. I know trimming the current or the capacitor will make sense, but I see no trimming on the layout of many chips. How can they make the frenquency stable? Is there any method to solve the problem without trimming?
Click to expand...
hi,
i can suggest you to read a paper by allen's student.
the paper is :
Process and temperature compensation in a 7-MHz CMOS clock oscillator
Sundaresan, K.; Allen, P.E.; Ayazi, F.;
Solid-State Circuits, IEEE Journal of
Volume 41, Issue 2, Feb. 2006 Page(s):433 - 442
Digital Object Identifier 10.1109/JSSC.2005.863149

good luck
jeff
 

54_1161683489.JPG


here is the schemetic. Vbias is from reference to get current to charge the capacitor C1 and C2. the output frequency will change a lot under different libraries, and it'll be worse if the temperature is considered.
 

How accurate do you want your osc?

If +/-10%~15% is good enough for you, then here is my method:
1. Build process/temperature/voltage compensated current source.
2. Build BGR.
3. Use MOS transistor as cap ( since the cap value variation is usually of the same phase of current source. That is, if you got larger current in FF, the MOS cap is also be larger )
4. Use the architecture similar to 555 timer. Use the voltage reference from BGR as H/L limit.
 

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    hktk

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I do not know what library you are using

But, I guess the value of C1 and C2 are fairly big.

Unfortunately, the freq of this circuit is very sensitive to Vbias, if you can post simulation result.

I will suggest you use a good BGR circuit to stablize the bias

By the way, I will not use this design for such a low freq oscillator
 

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    hktk

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Hi hktk, can u tell me more about this circuit, i think it's not complete, i'm working with oscillators and i'm interested in this one. Thanks
 

Hi hktk,

Check out some patents from national 6917249.
Basically, it's a very hard topic for doing PVT compensated oscillator. Most of the designs are based on RC charge/discharge. It's easy to get voltage and temperature compensation. It's difficult to get process compensation for those RC values.
Ppl always do calibration with a reference clean clock and automatically trim it step by step.
 

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