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References about digital DLL and a Verilog model

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newbie_1

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hi,

can you give me a clarification on dll? and what about phase interpolator, how can i use the interpolator? and good papers will be appreciated.

thanks a lot
newbie
 

dll loop verilog

here are some good papers
 

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    newbie_1

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design of phase interpolator dll

Hai arsenal,

Do you have any digital delay locked loop circuit papers or materials regarding digital DLL which can be implmented using the Verilog or Vhdl simulation tools completely .

Also can you tell any method by which i can use a Digital simulation tool (FPGA ADVANTAGE PRO) circuit output to GIVE to an analog simulation tool (Tanner/Tspice) signal circuit input ..
 

Re: about dll design

blowfish said:
Hai arsenal,

Do you have any digital delay locked loop circuit papers or materials regarding digital DLL which can be implmented using the Verilog or Vhdl simulation tools completely .

Also can you tell any method by which i can use a Digital simulation tool (FPGA ADVANTAGE PRO) circuit output to GIVE to an analog simulation tool (Tanner/Tspice) signal circuit input ..
Click to expand...

hi blowfish,

as to dll in verilog model, u can refer to the website of designers guide, also u can try write it by using counters, and u can try the attached one.

and after u get the dll model then u can use spectreVerilog to do the mixed signal simulation by creating a config view.
 

Re: about dll design

I am a beginner. Are there some good references for dll design? Thanks!:D
 

about dll design

Hi arsenal
how can I use your verilog model of dll?
Thank you!
 

Re: about dll design

zgz1983 said:
Hi arsenal
how can I use your verilog model of dll?
Thank you!
Click to expand...

u can just use it for simulation coz it gives only the behavioral model of the building blocks of dll, from which u can know what constructs a DLL and how it works.

thanks
arsenal
 
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    lexxvn

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Re: about dll design

May be this paper will be helpful
 

Re: about dll design

Hai arsenal,

There is some errors in the verilog code from stanford. Also some codes are missing in the submodules. Can you verify the working of code and post the good working code .
 

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