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handling max capacitance violations as part of Synopsys Flow

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pchimaku

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HI,
I have been trying to implement a large design. I have synthesized it using Design Compiler and then checked the initial timing in Jupiter without interconnect and found no max cap/ max trans violations. After placing the design in Jupiter ,I had some cap and transition violations . Using the macro placement from Jupiter and removing the std cell placement, I ran physopt in Physical Compiler.After the physopt I had a huge amount of max cap violations. My design met setup and had no trans violations
Could anybody please let me know how to correct these max cap violations.I hope to continue CTS/routing in Astro

Thanks
Pradeep
 

well, it doesn't need to worry about the cap violation, since your trans constrains were met.

anyway, check the physopt manual, there might be "-drc" option, which can fix design rule violation.

regards
 

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    pchimaku

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I've seen that often max capacitance violations were not fixed with an increamental compiler thus we wrote a script that find max_capacitance nets and breaks them into 2 or more paths buffering each one seperately. In our case this fixed the problem and didn't damage the timing
 
Re: handling max capacitance violations as part of Synopsys

Please make sure there are not dont_touch on the violations.
 

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