Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

What's the difference between always and assign commands?

Status
Not open for further replies.
C

choonlle

Full Member level 2
Joined
Jul 18, 2006
Messages
126
Helped
20
Reputation
40
Reaction score
1
Trophy points
1,298
Location
AFRICA
Activity points
2,025
what is the different between case1 and case 2?


case 1:
always (a)
begin
b=a;
end


case2:
assign b=a;
 

Re: always & assign

The difference between the two is that the design of case 1 is called behavioural modelling and that of case 2 is called data flow modelling.
Other than that the functionality is the same.
 

always & assign

very good

Added after 32 seconds:

I don't know

Added after 34 seconds:

Would you tell me what the difference is?
 

always & assign

Only syntax difference
 

Re: always & assign

choonlle said:
what is the different between case1 and case 2?


case 1:
always (a)
begin
b=a;
end


case2:
assign b=a;
Click to expand...

Case1 - "b" is a reg, Case2 "b" is a wire (you probably know that anyway). Functionally - meaning HW wise they are same. In simulation you may see some difference in 0-time behavior as the "always" block doesn't have to get executed at time 0 where as a continuous assign should. IIRC, tools used to have +always_trigger or some thing like that to avoid it, but lot of it is now outdated.

HTH
Ajeetha, CVC
www.noveldv.com
 

    C

    choonlle

    Points: 2
    Helpful Answer Positive Rating
Re: always & assign

that's means , in always statement, b must be register ?! do you think possible b is wire in always statement ?



Thanks!
 

Re: always & assign

choonlle said:
that's means , in always statement, b must be register ?! do you think possible b is wire in always statement ?



Thanks!
Click to expand...

Everything in an "always" statement must be declared as reg.
 

Re: always & assign

choonlle said:
that's means , in always statement, b must be register ?! do you think possible b is wire in always statement ?

Thanks!
Click to expand...

In Verilog a reg is misunderstood term - it need not represent a hardware "register" per-se. It can be a wire/combo gate output etc.

As the Verilog semantics/syntax has it, only a reg can be assigned procedurally (i.e. inside always/initial/task/fn etc.)

FYI - SystemVerilog has logic data type to avoid this confusion.

HTH
Ajeetha, CVC
www.noveldv.com
 

always & assign

the logic is the same, the only different is when input is
z or x value , the result is not the same!!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top