Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Cadence NC-Sim's stop / strobe ?

Status
Not open for further replies.

davyzhu

Advanced Member level 1
Joined
May 23, 2004
Messages
494
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,298
Location
oriental
Activity points
4,436
Hi all,

NC-Sim provide two main command to dump data: stop (-cont) and strobe.

My problem is which command is faster when used to dump data?

Thanks!
Davy
 

davyzhu said:
Hi all,

NC-Sim provide two main command to dump data: stop (-cont) and strobe.

I hope by "dump data" you mean "dumping/printing values of some signals/variables".

From ncvlog.pdf:

The strobe command is a Tcl procedure that uses the stop command to set a condition,
object, or time breakpoint and then, when the breakpoint triggers, executes a value
command to print out the values of the specified objects in tabular format.

So it is essentially the same thing, easier to use strobe I believe.

In general this debug approach is fine, but it depends on how many such commands you use, if you use only a few, it shouldn't really matter. If you use lots of them, I would recommend a review of your debug strategy - debug can be (and IMHO should be) built into testbench code as much as possible. We demonstrate such approach in our VMM adoption book, www.systemverilog.us

Idea is that a "transaction" should have pre-define display mechanism and the debug levels are deligently ued, controllable from a signle place etc. (Using vmm_log class).

Today I was attending AVM (Mentor) presentation, looks like they also have some thing similar, so clearly industry is moving towards this direction!

HTH
Ajeetha, CVC
www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 h**p://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar
 

    davyzhu

    Points: 2
    Helpful Answer Positive Rating
Hi aji_vlsi,

I am very interested in your idea. And fully agreed with your opinion "debug should be merged to testbench as much as possible".

And I cannot understand your sentence below. Is "transaction" mean "transaction level verification"? Do you mean "controllable from a single place" is "run one testbench"? And do you think how to determine the debug level? Thanks!

Idea is that a "transaction" should have pre-define display mechanism and the debug levels are diligently used, controllable from a single place etc. (Using vmm_log class).

Best regards,
Davy
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top