warning from spectre during circuit read-in

question 1:

"input.scs" 20: Illegal unit prefix "V" ignored.
"/home/cds/simulation/inv2/spectre/schematic/netlist/_graphical_stimuli.scs"
0:Illegal unit prefix "v" ignored.

Notice from spectre in 'pplus_u' :'R0' ,during hierarchy flattening.
R0.d1_r; Terminals are connected together ( to node ''vdd! ).
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All of above is the wrong message when simulating with spectre. what's wrong? It doesn't matter?

The 20th line of file "input.scs" is "V0 (vdd! 0) vsource dc=3V type=dc m=1"
And what is said in file "_graphical_stimmuli.scs" is "vin ( in1 0 ) vsource dc=3.75v type=dc"


question2:
i use spectre for simulatation. When post simulation, i add the word "extracted" in the environment options. But the plot seems to be no change. I don't know if it did do the post simulation or if the method i used was right. How can i know that spectre did do the "post simulation" ?

hello,
try removing the "v" from "vin ( in1 0 ) vsource dc=3.75v type=dc"

about question1:

try removing the "v" from "vin ( in1 0 ) vsource dc=3.75v type=dc"

Click to expand...

yeah, you are right. But does the wrong message should be worried about?

Notice from spectre in 'pplus_u' :'R0' ,during hierarchy flattening.
R0.d1_r; Terminals are connected together ( to node ''vdd! ).

Click to expand...

about question2:
Can someone tell me how to confirmation that the spectre did do the "post silulation"?

i use spectre for simulatation. When post simulation, i add the word "extracted" in the environment options. But the plot seems to be no change. I don't know if it did do the post simulation or if the method i used was right. How can i know that spectre did do the "post simulation" ?

Click to expand...

about the R0 thing i am only guessing that u are shorting some resistnace called R0, found in d1_r , do u have a cell view of that name "d1_r" , if so then try to see if u connected both terminals of the Resistance R0 to vdd.

safwatonline said:

about the R0 thing i am only guessing that u are shorting some resistnace called R0, found in d1_r , do u have a cell view of that name "d1_r" , if so then try to see if u connected both terminals of the Resistance R0 to vdd.

Click to expand...

oh, R0 are three terminals device. It's sub and one terminal are connected together to vdd. This connect is right for my schematic. May be, the message just wants to notify me?

About Q1:
It doesn't matter. But it looks better if you remove these warnings. You may either remove the unit 'V' (or 'v' ) or change them to "_V".

About Q2:
You can display the netlist to see which view is used for the simulation. Netlist extracted from "extracted" view will be quite different from that from "schematic" view.

Hughes said:

About Q2:
You can display the netlist to see which view is used for the simulation. Netlist extracted from "extracted" view will be quite different from that from "schematic" view.

Click to expand...

I have seen the netlist. After inserting the word "extracted" to eviroment option i got " Design cell view: schematic " in netlist. Does the method is right? There is a snap in accessory.

sophiefans said:

I have seen the netlist. After inserting the word "extracted" to eviroment option i got " Design cell view: schematic " in netlist. Does the method is right? There is a snap in accessory.

Click to expand...

You are right in setting the environment options, but I can't tell if you got the right netlist from the above information.

By inserting "extracted" before "schematic" in the "switch view list", the simulation view of the top cell will not be changed. It only changes views of cells used (directly or indirectly) by the top cell view.

Suppose your design is name whole_chip (cell name), which has three views: schematic, symbol and extracted. If you choose the simulation design as whole_chip/schematic, it will not changed to extracted view even if you set the "extracted" as the first switch view.

But you can use test circuit to simulation the design. For example, you can add a cellview test_whole_chip / schematic which calls whole_chip / symbol. Then you can select which view (whole_chip/schematic or whole_chip/extracted) is used by the netlister by setting "switch view list".

hi Hughes,
I have passed the post simulation in your manner. But why the method bellow which you have mentioned in your reply is not right?

1. Open up the test schematic for the inverter in edit mode. Under the Tools menu, choose Analog Environment. A window similar to the one shown below will pop-up.
2. In order for Cadence to simulate through the extracted view of the layout design instead of the schematic view, you will include an additional item (extracted) in the Switch View List such that it now contains the following:
hspiceS spice cmos_sch cmos.sch extracted schematic
3. You can now perform the simulation in the same manner as before, either via the Cadence or Hspice methods. This additional step allows you to take into account all the parasitic capacitances (eg. from interconnects and source/drain areas) that were extracted into the extraction view from your layout design. You may be able to notice subtle differences in the post-layout simulation results or waveforms as compared to the pre-layout schematic view results.

Click to expand...

copy from a certain manuel

Hi sophiefans,

I can't find the real problem. Could you tell me what's the real problem? That is, how is it not right? Does the simulation fail? Or it uses the wrong switch view? Or something other is wrong?

In the above examples, "extracted" is in between "cmos_sch cmos.sch" and "schematic". Normally we don't use "cmos_sch" and "cmos.sch", so the netlister will use extracted if it find one. But if a cell do have a "cmos_sch" or "cmos.sch" view, the "extracted" view will not be used. This is a possible problem.

In order to use "extracted" view, it should have the same pins as its symbol view -- both pin names and pin directions. Otherwise, the netlisting procedure will fail.

If the "extracted" view has global nets (such as "vdd!" and "gnd!"), sometimes these global nets will be treated as local -- may be a bug.

I can't imagine other problems now.

a) I personaly would NOT use the extracted view directly although I know people who do it.
I recommend to create (in case of DIVA) analog extracted view with parasitics and then use hierarchy editor to specify which view should be used in simulation.
It might be that syntax of extracted netlist is not in spectre language but in spice (or vice versa) and that it does not like that.

I don't know why i can't excute post simulation by invoking Analog Everioment in extracted view. There are three input signal which are given as the picture bellow. But while simulating, i can't go through. And the Status will always been shown as the picture bellow.

just an idea - are you using extracted made by DIVA for LVS???? if so then there should not be any difference between schematic and extrcated unless you include parasitics. For that we would have to see know if there are any pres or pcap devices in netlist. Then there must be a difference