Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Questions about phase detectors and loop filters in PLL

Status
Not open for further replies.

wylee

Full Member level 1
Joined
Feb 17, 2004
Messages
98
Helped
6
Reputation
12
Reaction score
3
Trophy points
1,288
Location
Malaysia
Activity points
1,031
I am new to PLL and would like to find out some answers below:

1. What is a full rate & half rate phase detector? which is better? is digital PFD a full rate detector?

2. Why do we use lag-lead loop filter in PLL? why not just lag filter (normal LPF)? is it for stability purposes?

3. Which type of loop filter is most commonly used? active lag filter or active PI filter & why?
 

Re: Newbie questions in PLL

wylee said:
I am new to PLL and would like to find out some answers below:

1. What is a full rate & half rate phase detector? which is better? is digital PFD a full rate detector?

2. Why do we use lag-lead loop filter in PLL? why not just lag filter (normal LPF)? is it for stability purposes?

3. Which type of loop filter is most commonly used? active lag filter or active PI filter & why?

2. It is for stability and also the lag-lead filter will introduce the a zero which will determine the damping factor of PLL second order syetem.

3. Active filter can be used to increased the overall loop gain of PLL and also place the pole and zero closer to the DC. Active PI quite common used
 

    wylee

    Points: 2
    Helpful Answer Positive Rating
Re: Newbie questions in PLL

i think half and full rate phase decetors are used in CDR "clock and data recovery"

but in PLL as a frequency multiplier or Frequency synthizer " usually use the charge PUMP with PFD

khouly
 

Newbie questions in PLL

yes half rate and full rate PD are PDs for CDR ,
i qoute:
The PLL implements a full-rate architecture because of its structural simplicity and operational robustness with regard to various data patterns. Compared with half-rate architectures [6], full-rate CDR requires higher circuit speed [7]. On the other hand, half-rate designs require high-speed multiphase clocks (or data) that need to be very well matched to avoid degradation in jitter tolerance. As a result, in full-rate CDR, the design of the voltage-controlled oscillator (VCO) is simplified and the physical layout of CDR can be very dense to minimize parasitics, which in turn helps to improve speed and reduce noise coupling.
In addition, the full-rate CDR generates a low jitter full-rate clock which is applied to a separate flip-flop to retime the data from the input amplifier.
this is from OC-192 serdes by broadcom for extra details i suggest Razavi's optical communication
 

    wylee

    Points: 2
    Helpful Answer Positive Rating
Re: Newbie questions in PLL

wylee said:
I am new to PLL and would like to find out some answers below:

1. What is a full rate & half rate phase detector? which is better? is digital PFD a full rate detector?

2. Why do we use lag-lead loop filter in PLL? why not just lag filter (normal LPF)? is it for stability purposes?

3. Which type of loop filter is most commonly used? active lag filter or active PI filter & why?

1.as i know, full rate and half rate phase detector are used in CDR circuits. the CDR circuits sense the input random data at full rate but employ a VCO running at half the input rate, this technique in phase detector called half-rate architechture, which relaxes the VCO design.
otherwise is full rate phase detector.
jeff.yan
 

Newbie questions in PLL

Its seems that using charge pump PLL architecture is quite common practice nowdays.

Instead of using active/passive loop filter, charge pump with a cap replace that block. What is the advantage & disadvantage of using a charge pump in PLL?


In the case of PFD, the PFD I always came accross is 2 DFF and AND gate. Is there any other improved architecture designs around?
 

Re: Newbie questions in PLL

wylee said:
In the case of PFD, the PFD I always came accross is 2 DFF and AND gate. Is there any other improved architecture designs around?
 

Re: Newbie questions in PLL

wylee said:
Its seems that using charge pump PLL architecture is quite common practice nowdays.

Instead of using active/passive loop filter, charge pump with a cap replace that block. What is the advantage & disadvantage of using a charge pump in PLL?


In the case of PFD, the PFD I always came accross is 2 DFF and AND gate. Is there any other improved architecture designs around?

Im my opinion,

i guess when u use PFD, there are 2 outputs compare to stand alone phase and frequency detector (1 output). With 2 outputs, u need to have 2 current source (chargepump) controlled by these 2 output to charge and discharge the capacitor. By the way, the charge pump and the capacitor serve as loop filter for the PLL.
 

Questions in PLL

I recently read up about "Dead Zone" faced in PFD.

Is "Dead Zone" the only big problem in designing a PFD?

Here is a report done by student (i think) i foung on web,
which use a delay chain to minimizie dead zone in classical PFD (2 DFF, 1 AND type PFD)
**broken link removed**

Can anyone sugguest me any new PFD architecture/papers which minimize/cancel this phenomena?
 

Questions in PLL

i think the solution used is adding a delay in the reset path (either by inverter chain or by introducing a large cap. load), this wil decrease the dead-zone but it can introduce something called blind-zone , but as far as i could remember that the blind zone will affect only the settling time so if it is not a big spec on u then it is no problem
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top