placement optimization for two PLL modules in a SOC design

We have two PLLs (TSMC IP) in our SOC design. Acordding to the application note, there are some placement rules for one PLL. We'd like to know that is there any specical consideration for the placement of two PLLs. It would be better if there are some practice examples (layout floorplan).
Thank.

Re: placement optimization for two PLL modules in a SOC desi

add guard rings between the plls and digital side... in general place the pll on the corner that is easy.. ensure the switching of pll does not cross talk the digital side..

Regards
Shankar

Hi,

Likely ther PLL already has guard ring inside it, and thus don't need another guard ring. By the way, it is impossible to put guard ring with P&R tool, unless there is a macro for this, but then rather put this in the PLL itself.

Depend on how you intend to use the pll. If they are independ of one another, then there is not additonal constraint. If you use them to cancel the clock insertion delay and one PLL is double the freq of the other. then there are plenty of things to take care of; too much detail to mention here, and is very design dependent!

Regards,
Eng Han
www.eda-utilities.com

Re: placement optimization for two PLL modules in a SOC desi

No we can manually add guard ring using Astro tool we did this for last chip...

its not necessary to add guard ring in the analog block itself..

Re: placement optimization for two PLL modules in a SOC desi

leeenghan said:

Likely ther PLL already has guard ring inside it, and thus don't need another guard ring. By the way, it is impossible to put guard ring with P&R tool, unless there is a macro for this, but then rather put this in the PLL itself.

Depend on how you intend to use the pll. If they are independ of one another, then there is not additonal constraint. If you use them to cancel the clock insertion delay and one PLL is double the freq of the other. then there are plenty of things to take care of; too much detail to mention here, and is very design dependent!

Click to expand...

Thanks, leeenghan.
You're right, the two PLL are independent for each other, they offer different clocks for different logics in the SOC.
What' about the power up sequence for the two PLLs? Should they be power on at the same time?

Added after 8 minutes:

shankarmit said:

No we can manually add guard ring using Astro tool we did this for last chip...

its not necessary to add guard ring in the analog block itself..

Click to expand...

Hi shankarmit,
You means that additional guard ring would be better, is that right?
The PLL IP has guard ring inside, and has some place&route rules to comply. But you still add guard ring for it. Would you please tell me why?

I'm also intrested on how to add guard ring using Astro
Thanks

Re: placement optimization for two PLL modules in a SOC desi

Hi,

I don't think the power-up sequences matter. You design has to assume that the time for the PLLs to lock are different, and even the phases are different (even if the input clock are the same).

Regarding adding guard ring to the PLL, I think it is a job for the customer layout. Why? The knowledge to put in the guard ring is not needed for a digital layout engineer, but is at the finger tip of a customer layout enginerer. To put in the guard ring, you will need to know:
1. How far should you guard ring be away from the PLL abstract.
2. As the abstract typically does not capture nwell, p/n-diffusion information, you have to view the full gds to figure (1) out (another set of tool needed here!)
3. You have to know well spacing, diffusion spacing, contact spacing.
4. You have to decide to use single guard ring or double guard ring
5. You have to decide to use one row of contact, or multiple row of contact in the guard ring
6. The guard ring has to tie to quiet VDD and VSS. The power from the digital domain should not be use. What happen if the quiet power in the PLL is not brought out as a pin?
7. You cannot (or difficult to) merge any part of the top level guard ring (the one we are talking about) with sub-block guard ring (those part of the sub-block gurad ring that happen to be also at the side of the PLL boundary), and thus there is significant area wastage.
8. If you are using Magma or SOC, you cannot add guard ring. What happen in the middle (or the next revsion) of the project you have to switch tool, and suddenly find that you have to now change the PLL layout to add the guard ring, and then re-generate the LEF.

Regards,
Eng Han
www.eda-utilities.com

Re: placement optimization for two PLL modules in a SOC desi

Hi leeenghan,
Thanks for your detailed answer.
I think the guard ring design is beyond my job, and what I concern about are the multi-PLL application as black hard macro, the system level consideration(power up sequence) and the floorplan consideration.

Regards,
albred