Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

What is the inter and intra delay in Verilog?

Status
Not open for further replies.
ananth_anbu

ananth_anbu

Newbie level 4
Joined
Feb 12, 2006
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,333
verilog question

Hi,

what is inter delay and intra deay in verilog? ple explain?
 

Re: verilog question

They are similar to inertial delay and transport delay in VHDL respectively.
Check VHDL book Perry for the explnation.
 
  • Like
Reactions: optimuz

    ananth_anbu

    ananth_anbu

    Points: 2
    Helpful Answer Positive Rating
    O

    optimuz

    Points: 2
    Helpful Answer Positive Rating
Re: verilog question

Inter Assignment Delay is most commonly used delay
It simply wait for appropriate no of timesteps before executing the command.
#10 q = x + y;

Intra-Assignment Delay (Used in data flow modelling)
q = #10 x + y;

The value of x+y is stored at the time that the assignment is executed, but this value is not assigned to q until after the delay period.
 
  • Like
Reactions: optimuz

    ananth_anbu

    ananth_anbu

    Points: 2
    Helpful Answer Positive Rating
    O

    optimuz

    Points: 2
    Helpful Answer Positive Rating
verilog question

Check Verilog book by Samir Palnitkar. It is given quite nice in that
 

    ananth_anbu

    ananth_anbu

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top