Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

drc error for semi-custom design

Status
Not open for further replies.
siva_7517

siva_7517

Full Member level 2
Joined
Jan 16, 2006
Messages
138
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
2,401
hi,

I am doing a asic semi-custom design. While doing a drc check in virtuoso, i put a exclude layer on the standard cell to avoid the tools to check the standard cell. This means im only checking the drc for interconnection between the standard cell. Eventually, i still have a errors after doing the drc check. The error is which is violated the rules are :

Via1 size = 0.26 * 0.26
Minimum MetalTop line width = 0.44um
All contacts must be covered with metal1
minimum poly overlap of contact > 0.10
minimum island overlap of contact > 0.10


Can anyone guide me on how to overcome this problem?
And another thing is, can anyone give the proper step to do a drc check.

Thanks in advance

siva
 

hello Shiva

could u please tell which DRC checks u are following i mean r using any other tool for DRC , if u r using mentors calibre . i can definately help u .there should not be much prob even if ur using Diva r Dracula rule files . so in any case let us know the procedure


suresh
 

    siva_7517

    siva_7517

    Points: 2
    Helpful Answer Positive Rating
Hi,

Sorry for the incomplete information.
Well, i am using Diva, Cadence to do the DRC check.

Siva
 

hello Shiva,

Since you are using Diva rules file, there are actually not many options to check according to our needs. But there is one way to do so, you can go to the rules file and comment the rules which check VIA and others and then perform DRC, now the tool will ignore all the vias .

I hope it works and this is all u wanted ,


suresh
 

Hi siva,

You can maually edit the routing.. for example for minimum spacing extend the metal were it show error ensure that it does not metal spacing...

similry for via ... this is via size specified in runset ... create via in smae size ....


Regards
Shankar
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top