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How can I include a vhdl project which has a clock into Actel A3PE-EVAL_BRD1?

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mobile-it

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Anyone has some experience with this board?

I have difficulties with assigning pins to signals.

The clock is pin 26 or am I wrong?

When I download the stapl file from the examples into my fpga everything works fine, when I write my own vhdl file I can program my FPGA but it is not working.. I think this may be because of wrong clock assignment.. can anyone help me out?


thanks very much!
 

Re: Actel A3PE-EVAL_BRD1

Can someone please help me out?
 

Re: Actel A3PE-EVAL_BRD1

Nobody seems to have an answer to my question?

Can someone deliver me a step-by step manual how I can include a vhdl project wich has a clock into my actel fpga? especially the pin assignments... That will help me a lot. Does nobody work with Actel fpga's at this time???
 

Actel A3PE-EVAL_BRD1

First steps in your rationale should include the testing of the clock oscillator and if it goes to the right FPGA pin. It is an easy task!!, I have downloaded the schematics and you have a jumper (JP24) and the FPGA uses a flat pack package so you can test the FPGA clock pin.

First verify this and afterwards you may check your Actel design (sthg that should be trivial).
 

    mobile-it

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Re: Actel A3PE-EVAL_BRD1

Thanks for your help... stupid I was not thinking about this myself...

I will check it soon.
 

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