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The offset for circuits such as op-amp depends on the mismatch between various circuit components. This offset can be estimated based on the mismatch data provided by the fab. Normally, the fab would provide the mismatch data for transistor pairs laid down in specific layout schemes. Seeing the data, the designer can decide the best possible layout configuration and transistor size for best offset performance. You will have to check the fab's mismatch data for all components such as transistors, resistors, capacitors that are used in your circuit.
Sometimes, error in biasing and incorrect sizing may lead to offset [Ex: Basic 2 stage op-amp]. The only solution to avoid such offset is careful design.
Hand analysis is done using the mismatch data available. Offset simulations are done by running monte carlo analysis on the statistical models of the components, where in the random variation of various parameters of the components is present.
The biasing, sizing of critical transistors and layout are done accordingly looking at the offset spread(will be a Gaussian with zero mean for circuits with no systematic offset) and knowing the desired max offset.
As a rule of thumb any technologie has a certain offset intrinsic per um .
The offset of a diff input pair is proportional with 1/sqrt(W*L) so ..the first aprox you can do is : biger area means lower offset
The layout can increase this or keep it more or less ct.
So basically two things affect the calculation of offset voltage; First is W & L mismatch and second is threshold voltage mismatch. So W & L mismatch can be reduced by increasing area. What's abt threshold voltage mismatch? How can it be reduced? Does it depend on the area?
So basically two things affect the calculation of offset voltage; First is W & L mismatch and second is threshold voltage mismatch. So W & L mismatch can be reduced by increasing area. What's abt threshold voltage mismatch? How can it be reduced? Does it depend on the area?
Common centroid layout should take care of most of it. Takes into account termal and distance gradients. If you need a better matching, you might want to use 2nd order common centroid
Vt is a 'constant' given by the technology. it depends on a lo of factors and a bigger area and matching helps. I think that this paper will explain a little more about Vth mismatch
h**p://lhc-workshop-2004.web.cern.ch/lhc-workshop-2004/1-Plenary%20sessions/11-anelli_proceedings.pdf
You can simulate offset setting to one group of mosfets W/L ratio higher than nominal and other less... >Just have to think what is the worst case...
How much is depends on technology specification, and previous experience...
For example measure offest of fabricated opamp and see how much should be ΔW and ΔL to produce such offset.
You need first the technology info. Then you need Monte Carlo(statistical) models from the technology/design package. After that is easy, you do a monte carlo simulation and get the value and standard deviation=sigma. I guess you need for standard design +/- 3sigma
there give you a experience formula:
in 0.25um process ,the offset can be calculated like this
Voff=30mv/sqrt(w*l). for +/- 3sigma
Voff=90mv/sqrt(w*l). for +/- 1sigma
dont make the number of input pair too more, it will cause the system offset larger.
M=8 is enough.
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