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the bandwidth simulation for the opa+inverter

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chang830

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Hi,
I am designing a CMOS circuit composed of a OPA+cascaded inverter buffers. This circuit is to ampify a weak signal and bufferd it to a CMOS signal. I wonder if I want to get the bandwidth of this signal, how can I to do the simulation?The ac simulation can do it? It is more like a mixed analog digital circuit, I have some puzzles on it.

Thanks
 

Hello:

Real puzzle is really in the DC levels:
Where is the input analog ground (or "common mode voltage")
let's say VDD/2;
when a small voltage dV above that (i.e. VDD/2+dV) ==> output goes VDD
when a small voltage dV below that (i.e. VDD/2-dV) ==> output goes 0

well most of the case, without careful treatment of DC voltages of all circuit,
that won't happen.....the high gain transition point won't be exactly VDD/2.

Good Luck!
 

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    chang830

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Bias your circuit correctly, make sure the DC operation point is right. You can design a simple feedback circuit to fixed the operation point.
 

dear all,
I think maybe I did not express my questions clearly. Here, my concern here is for the circuit I cited, i.e., the opa+inverter, it is in fact a mixed signal circuit. The ac analysis is meaningful for the -3dB bandwidth estimation? Or I should monitor the transisent analysis to assess the bandwidth?

Thanks
 

Suppose we are careful enough.
I see no reason why these two method
should predict different bandwidth.
 

jcpu said:
Hello:

Real puzzle is really in the DC levels:
Where is the input analog ground (or "common mode voltage")
let's say VDD/2;
when a small voltage dV above that (i.e. VDD/2+dV) ==> output goes VDD
when a small voltage dV below that (i.e. VDD/2-dV) ==> output goes 0

well most of the case, without careful treatment of DC voltages of all circuit,
that won't happen.....the high gain transition point won't be exactly VDD/2.

Good Luck!
Click to expand...

hi,jcpu,
thanks for the reply!

I think I begin understand what you mean.

Assume a three inverter cascaded circuit,if I can carefully bias the three inverters at its high gain region,i.e.,set the input and output at VDD/2,then I can do the ac analysis now and get the bandwidth from the simulation easily.

Then I remove the input and output bias voltage away, and inject a clock signal(0-vdd CMOS level), you mean the max freq(bandwidth) of clock signal is consistant with the above AC analysis results?

Thanks
 

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