Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

REG case statement in verilog

Status
Not open for further replies.

samuel_raja_77

Junior Member level 2
Joined
Apr 8, 2006
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,458
case within case

1.can we use a case statement within a case statment like the one described below
e.g.
case(state2)
1:begin
case(state1)
1:begin
end
2:begin
end
endcase
end
endcase
2.will it be synthesizable and i am using this code for fpga design .......and will there be any back end problems if so what is the solution
 

case statement in verilog

This is perfectly alright.
 
  • Like
Reactions: bardia

    bardia

    Points: 2
    Helpful Answer Positive Rating
verilog syntax case statment

there should be no problem in back end. I beleive!!
 
  • Like
Reactions: bardia

    bardia

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top