Questions About VHDL process

My program with two processes are as following:

process ( CLK )
begin
if (CLK'EVENT and CLK = '1' )then
ADDR := ADDR + "0000000000000000001";
elsif ( RESET = '1') then
ADDR := "0000000000000000000";
end if;
CEN_ADDR <= ADDR;
end process;

process ( CLK )
begin
if ( CLK'EVENT and CLK = '1' ) then
if ( RESET = '0') then
RREG1 := DATA1;
RREG2 := DATA2;
RREG3 := DATA3;
REG1 := RREG1;
REG2 := RREG2;
REG3 := RREG3;
OUT1 <= REG1;
OUT2 <= REG2;
OUT 3 <= REG3;
end if;
end if;
end process;
O_DATA1 <= OUT1;
O_DATA2 <= OUT2;
O_DATA3 <= OUT3;

I want to use two current parts to do the followings:

1) currently process CEN_ADDR and O_DATA1, O_DATA2 and O_DATA3.
2) Send out CEN_ADDR right away without delay, and O_DATA1, O_DATA2 and O_DATA3 are delayed for two cycles.
For O_DATA1, O_DATA2 and O_DATA3 can reach Data bus at the same time, I put them out
from process.
Do you think O_DATA1, O_DATA2 , O_DATA3 can be updated correctly with the input DATA1,
DATA2 and DATA3 ?
Or O_DATA1, O_DATA2 and O_DATA3 are send out right away without updating?



Thank you for your help.

sorry pal but there is too many mistakes in your code and they are as follows:

1-you didnt define the variables (ADDR in the first process) (REG1,REG2,REG3 in the second process).

2-at the first process if you watch carefully your code you will always get

ADDR<="0000000000000000000" because the process will start again in the falling edge of the CLK and it will always complies with the else claus of the if statement.

process ( CLK )
begin
if (CLK'EVENT and CLK = '1' )then
ADDR := ADDR + "0000000000000000001";
else
ADDR := "0000000000000000000";
end if;
CEN_ADDR <= ADDR;
end process;

3-variables are the worst thing to use when you work with VHDL(alwas use signals not variables)

4-in the second process i dont find any meaning for the first three lines since the following three lines will override the first three lines.


sorry to say that but your code is completely incorrect...u need to read more about VHDL and i advice you to read ("VHDL for programmable logic" by kevin skahil)

good luck

So sorry.

I change it from original one.

If I only use signal in process, does time delay matters?

process ( CLK )
begin
if (CLK'EVENT and CLK = '1' )then
ADDR := ADDR + "0000000000000000001";
elsif ( RESET = '1') then
ADDR := "0000000000000000000";
end if;
CEN_ADDR <= ADDR;
end process;

Click to expand...

here i dont find any issues...provided all the signals,variables are defined globally...
the process will be called on both the edges of the clock...only on risingedge it ll incr the addr...ur reset is synchronous to ur clock...and the CEN_ADDR will be latched on both the edges of the clock as it is used inside the process without any conditional statement to control it... this might cause implementational problems

process ( CLK )
begin
if ( CLK'EVENT and CLK = '1' ) then
if ( RESET = '0') then
RREG1 := DATA1;
RREG2 := DATA2;
RREG3 := DATA3;

Click to expand...

this will happen at the first clock

REG1 := RREG1;
REG2 := RREG2;
REG3 := RREG3

Click to expand...

;

this will happen at the second clock

OUT1 <= REG1;
OUT2 <= REG2;
OUT 3 <= REG3;

Click to expand...

this will happen at the third clock

end if;
end if;
end process;
O_DATA1 <= OUT1;
O_DATA2 <= OUT2;
O_DATA3 <= OUT3;

Click to expand...

this will happen whenever ur OUT1-3 is updated...
i dont understand why u used different logic levels for reset in ur processes...
in ur first process ur reset follows 1
in ur second process ur reset follows 0 why???

Reset should be '1' for all so sorry for my mistake.

for the first process. If I change it as following, it is going to make it better?

process ( CLK )
begin
if (CLK'EVENT and CLK = '1' )then
ADDR := ADDR + "0000000000000000001";
elsif ( CLK = '1' and RESET = '1') then
ADDR := "0000000000000000000";
end if;
end process;
CEN_ADDR <= ADDR;

Thank you.

To electron_boy

first to electron boy u said that variables can be defined golbally and this is incorrect......variables can be only defined within the process not outside

but to EDA_hg81 you can modify the code as follows for the first process

signal ADDR : std_logic_vector(18 downto 0); --this defined after architecture
--declaration and before begin

process ( CLK, RESET )
begin

if(RESET = '1') then
ADDR <= (others => '0');
elsif (CLK'EVENT and CLK = '1' )then
ADDR <= ADDR + 1;
end if
end process;
CEN_ADDR <= ADDR;

good luck
[/quote]

thank you all