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About single loop multibit delta-sigma modulators

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bob_lv

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multi bit single loop sigma delta

used in fractional-N frequency synthesizer
i can't understand the multi-bit quantizer,for a 16-bit modulator,how many bits the feedback is? Is it ture that the MSBs of the last accumulator output is the quantizer output and the feedback is the remaing LSBs?Is the bits number of the feedback the same with the input?
i'm all confused!
who can give me some help?Thaks very much!
 

pll multi-bit quantizer

It is true!

The MSB part is the output. The LSB part is the feedback. The most simple architecture is if only the feedback contain a time discrete filter. The LSB and the MSB together form the input.
 
examples of single loop transfer function

Then how about the range(number of bits) of the input and the feedback?And how to decide the range of every accumulator output?Only the range is known,then the bits of accumulator can be confirmed.
 

single loop sigma delta

The feedback filter should be designed so that the noise shaping function is

(1-z^-1)^n

If the MSB contain more than one bit the divider should have more than two divisions. if you simulate the modulator you will find gaussian distribution of the ouput numbers which help to reduce spurious tones. A high order increases the total noise power and the phase excursions of the PLL.

I give you only hints not a full solution. That should stimulate to understand the properties of the modulator in more detail. A good starting point is to derive from the above noise shaping transfer function the feedback filter transfer function. So you understand at what node the uncorrelated truncation noise is injected in the modulator loop and how it is shaped. If you have written down the equation you can setup a simulation script for the modulator and try different bitwidths and filters. The papers are only a starting point. What is today implemented in IC you will see in 2-3 years as patents.
 

multibit sigma-delta

Thanks!
My design is for multi-modulus divider,so I need multibit modulator.But there's few documents about multibit modulator or too brief.
If the last accumulator output 16 bits ,the 4 MSBs is used for quantization output,is the feedback just the remaining 12 LSBs or need some other MSBs?
And can you show me some help or recommending some papers for simulation of the multibit modulator?
 

single loop dsm

It is as you described. The 12LSB have to feedback. The closed to actual implementation optimisation paper is here:
 
multibit delta-sigma

In the first paper, the NTF(z)=(1-z^(-1))^3/(1-z^(-1)+0.5z^(-2)), and the STF(z)=z^(-1)(4-5z^(-1)+2z^(-2))/(2-2z^(-1)+z^(-2)),and it said the 5-MSBs is the quantizer output, the left LSBs is feedback. So the feedback should be -E(z),so (K+E(z))H(z)+E(z)=out, the NTF(z) is the same with the paper,but STF(z) I got is z^(-1)(4-5z^(-1)+2z^(-2))/2(1-z^(-1))^3, it's not equal to the result of the paper. Am I wrong?
And I don't know how to simulate it with matlab. the output is binary, the main problem is I don't know how to deal with binary numbers in matlab.how to express the 5 MSBs and left 11 LSBs? I use command ' bitget' , but I can't change the binary number to decimal number. it need to feedback to input ,then is subtracted.
 
single loop matlab functions

Did you have access to Matlab. I could give a small example with the above transfer function. It takes a day because I busy now.
 
multi bit delta

Thank you very much! I've done some simulations with matlab today, but unfortunately the result is wrong.
I need the matlab examples about this . My emai is lv0223@163.com
 

multibit sdm matlab

You can do it with simulink.
 
single mash delta sigma

In simulink, I don't know how to deal with the output and feedback.
 

multi bit sigma delta

Here is a Matlab script which compares different filter architecture for multibit sigma delta modulators. If you find this script usefull please donate help points.
 
multi bit single feedback delta sigma

The problem I didn't understand is still the about the quantizer. For example, NTF=(1-z^-1)^3, the output range is from -3 to 4, why can it use 1-bit truncator? If use multibit truncator, how does it express this range?
Yours is a error-feedback structure. the structure in the paper a_cmos_monolithic_sigma_delta_controlled_fractional_n_frequency_synthesizer is like what I want to use. It is a CIFF sturcture. But is seems like it also uses truncator as a quantizer! This is what I don't understand.
 

delta sigma multibit

The truncation in the scrips file is based on the "floor" function. So only integer are passed to the output and the remainder is feedback in the filter. The script should demonstrate the noise transfer function, the poles, the number distribution and the spectrum of the number distribution. Please also try different input numbers. You will see that some numbers gives strong spurs. That will require an addtional dither generator operating on the smallest LSB and is not included in the script simulation.
 
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    bob_lv

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delta sigma ntf in pll

Thanks again for your help!
The modulator is just some adders and registors, so how to realize the circuits? I means, use hdl code or directly use stand cells to build it or other methods？
 

mash matlab

Try to work as long as possible in the Matlab script enviroment. The next step is to adapt the bittrue implementation in Matlab. Then analyse the modulator with the PLL together. That requires further models for analog components. If the Matlab model is very similar to the implementation you path to VerilogHDL or VHDL. If direct plan to built the logic w/o synthesis the VerlogHDL of VHDL helps to compare the implementation. Use a well testet Matlab testcase trough all description languages.
 

error feedback delta-sigma modulator

Hi,rfsystem
With your help, I've simulate the single_loop DSM in Matlab, but I dont't know how to adapt it for the bittrue implementation in Matlab. Can you show me some cues?
I've simulated 3-order MASH DSM with bittrue Matlab code(it is merely 3 accumulators). But it takes over 5 minutes to simulate 2^14 points with 16-bit input. Is it too long?
 

single loop delta

Hi bob_lv,

I did not have the script in front of me but I think it operate in the limited integer domain. I am not shure about the signed or unsigned numbers. I think the script mixed some of these. The simulation result should be bittrue.

Did you make any modification to convert to bittrue? I think the newer Matlab releases support integer arithmetic. I mimic the integer behaviour with ceil and floor functions and make shure that via scaliing or some other operations the integer domain is not leaved. So Matlab is fast if everthing for him/her is an double.

Do you use the modulator for a PLL?
 

pll sigma delta multi bit single loop

yes, I use it for a PLL frequency synthesizer. I have simulated the MASH DSM in modelsim, it's just 3 accumulaors,the input is unsigned number. The result is the same with expected.

But for multi-bit high order DSM, I don't know the input and output are whether signed or unsigned, and for a 3-bit DSM, how to use the 3MSBs as output? I've tried to write some verilog codes, but all the results are wrong. And I can't find any clues.

The input is a fractional number between 0 and 1, but the output may be between -1 and 2, so how to realize it without using float operation? For example , I use 16-bit input as a fraction , after some operations, the result may be 20-bit, so how to use the MSBs as integer output?
 

multi bit quantizer in matlab

I wrote a verilog code. The input is a 20-bit signed number.The 4 MSBs is the integer part, and the other 16 LSBs is fracional part. Input of the quantizer is also 20 bits, and 4 MSBs as final quantizer output. As a result , when the input is between -3 and 2, the result is right. When I use 5-bit quantizer,the stabel input range is between -6 and 3.5. I think they are too narrow! Is it reasonable?
 

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