dsp peripheral for higher sampling frequency

I'd like to ask you a question about some dsp
capabilities. In the book "DSP and applications
with the C6713 C6416 DSK" the author says that
the sampling frequencies supported by the AIC23
codec are 8, 16, 24, 32, 44.1, 48 and 96 kHz
(using DSK6713_AIC23_FREQ_fsKHZ).
But my GSM modulator design with 271 kb/s rate
with the use of an intermediate carrier frequency
which all will require the use of sampling frequency
of about 3 MHz or even more. But how can it be realized
to get the output signal with such a sampling rate.
Maybe there's another way to set the sampling frequency?

Maybe I need some kind of a peripheral to get such a sampling
frequency. Please what can I do?

these codecs can not ptoduce these frequencies. so you need an separate A/D converter, inserted to the DSP's external bus (i/o bus, memory bus). Manufacturers make ADCs up to 200MHz...1GHz, i think.

How can I set the sampling frequency after I
add on an external a/d d/a converters. I mean the
routine in the CCS.

usually, whe use a timer interrupt, with the sampling frequency.
in the timer ISR we make a reading from the ADC, and next make a samping command, to start the conversion for the next timer IT. Some ADCs have 2 addresses: one for data reading, and one for the sample command.

Please could you upload me some practical
materials and literature concerning the point

we used at the university, a dspcard, what they (a teacher) designed, and said us, that method. i do not know about any materials in things like that. i looked for similar things, but everywhere are just teorethical papers, and books.

here is an assembly project for that card. a littlebit bugy, and you cannot use without this card. i do not have schematics about the card. it is a PC oscilloscope.
in the szkop.asm , you will find some things. in the card is a TMS320VC5402-100 DSP, and an ADC, up to 1,5MHz. i do not know the type of that, and more about that card.

i think it is very simple. just use a 3state bus driver, an address decoder (FPGA, CPLD), and connect the adc's data lines, with the bus driver to the DSP's external bus if. and the address decoder will control the bus-drv, and the adc's sampling pin, in another addresses case. this 2 addresses thing -what i wrote- is not in the adc, but in the card

Added after 1 minutes:

i tried to upload/attach a zip file, but i do not see it.

Hi,
Last message related this topic is seen on 24 Oct 2005.

Now I have similar problem. Do you want to say anything to me ))):

Best regards.