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how to use virtual clock inDC

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sdc virtual clock

virtual clock is not a real clock, ti is used to constrain design
 

dc virtual clock

Hi

Please check this post:


Hope this helps
 
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    ivlsi

    ivlsi

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constraint virtual clock

dc use virtual clock to constraint combinational logic .
it has no souce , just an ideal clock waveform . In my opinion, it can be replaced by set_max_delay
 

dc中virtual clock的应用

Virtual clock is used to constraint I/O in much better then max delay.

In a SDC it can be defined as a clock waveform which is not associated with any port.

create_clock -name "clk_virtual" - period 10 -waveform {0 5}

I think most of the industry tools understand SDC:!:
 

virtual clock

the discuss above is good, thanks everyone.
 

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