power planning in SOC Encounter

encounter power ring

Hi guys,

Does anyone know what is the role of thumb for power / ground ring width? some one told me 1 um for each 1 mA current consumption. Is it true? What about the number of power strip in die size? Is there any role for it?

Regards

soc encounter power planning

how many power strips are needed is up to your chip's

power consumption and operating frequency. the higher

power, the more power strips are needed, the higher

operating frequency, the more power strips are needed.

best regards

omid219 said:

Hi guys,

Does anyone know what is the role of thumb for power / ground ring width? some one told me 1 um for each 1 mA current consumption. Is it true? What about the number of power strip in die size? Is there any role for it?

Regards

Click to expand...

powerplanning concepts of asic

Different technologies are different. Read the design rule document from the foundry there will be the sugestion.

In most cases, it is hard to estimate the current on the power ring when you are routing. Make it as conservative as possible..

soc encounter vcd poweranalysis

omid219,

Does anyone know what is the role of thumb for power / ground ring width? some one told me 1 um for each 1 mA current consumption. Is it true? What about the number of power strip in die size? Is there any role for it?

Click to expand...

In power ring, you usually have several power pads on every bond side. Assuming the most commonly used methodology is to have a power pad and a gnd placed side by side per bond side, thus the average length between adjacent pairs of power-gnd pads (between any two bond sides) is about 1/4 chip perimeter. I hope you can visual or imagine the concept.

The worst-case scenerio is the power that will eventually be fed into the cells at the centre of the die. Due to high I-R drop, the power ring itself must as far as possible consumes minimum power dissipation of not more than 0.05% of the entire chip.

To achieve this, expand all your power width of all branches as much as possible.

Usually sheet resistance of conductor is 0.04Ω/sq. Therefore the wider your width, the better since R = L/W . Rsq

Most important rule of thumb is to avoid Electromigration. To achieve, you need to make sure that the peak current density must be well below 0.1A/mm2


In practice, you need to know how many levels of branches for your power distribution network.
Assuming 6 levels (regardless Star, Tree, Bus, Grid, Split etc), use the widest width (about 24λ) on the first level starting from the power ring (inclusive). The next level branch, reduce the width by 1/2 until you get 4λ as Vdd rail to the CMOS inverters.
To make it more effective, you can increase from 24λ to 48λ, provided the Vdd rail in the logic cells permit 4λ to 8λ.
If your I/O pads are more than sufficient, you can include more power-gnd pairs per bond side to reduce the inter-length between adjacent pairs of power-gnd pads.
Another way is to minimise branch length in logic domains, blocks and cells, so as to minimise I-R drop per branch, thus minimises static power consumption and also reduced heat dissipation per mm2.

encounter power strips

Hi SkyHigh,
Thanks for the answer.
I learnt at my school that
The width of the straps, core ring etc., are calculated from the power report generated from vcd file obtained from simulation.
but ur explanation is quiet different.
Would u pleasee take an example and explain it?
I am interested in power analysis that
how do u do EM check and IR drop analysis.
If possible please elaborate on EM check.

I think u got very good experience on this.
Would u pl tell me about the issues we usually face during power planning and
how to take care of them in early stages?
Pl help

Thank u in advance.
Sowmya