How to slowdown the rise time of an off-board signal?

how to reduce the signal rise time

I need to send a 40MHz signal from one board to a
FPGA board.

The cable is less than 1 feet, could be made
as short as 6 inches. But the total length
including onboard trace will still be
about 1 feet.

I am pretty worried about the risetime,
it is about 2ns.

This risetime will give me certain
reflection and that will ruin my waveform.

So I am thinking slowdown the risetime by
either one method:

1. add a low-pass filter
2. add a shunt capacitor to absorb the
fast slewing current.

Currently I prefer the second one, which one
do you think better? and do you have other
thought on this problem?

Thanks a lot! enjoy

Hi greenfrog,

Both method 1 and 2 are about the same. Your cable is basically RLCG, with R and L dominating other electrical parameters with such a length like 1 ft long.

Method 1 - If you use a 1st order passive low-pass filter, it will be the similar to method 2. So you can have nth order passive or active filter. However the order here doesnt matter.

Method 2 - Adding a shunt capacitor is creating a 1st order passive low-pass filter or a series-shunt RC filter because your cable already has resistance.

From both methods you proposed, there is one thing in common, the shunt capacitance and series resistance. From any electronic design publications, one common way to reduce rise time or one common design problem that limits the rise time is shunt capacitance and series resistance.

The larger the shunt capacitance and series resistance, the longer the rise time because we know time constant = RC.
The formula for rise time (10% to 90%) is 0.63 RC.

Another method is to use a unity-gain buffer or voltage follower followed by a sample-hold circuit. Hence you can eliminate reflection and impedance mismatch on the transmission line (cable) and you can synchronise by means of a clock when you want to sample your signal from the buffer.

Hi, Skyhigh:

You are right, that the both methods are basically same. But I just feel that the a series ressitor won't make much difference, because here it is the slew current which decide the risetime in my case, thus a resistor will not
affest this slew current. That is what I think.

I also think that the risetime of 10% to 90% is about
2.2RC other than 0.63RC, .

I think for one feed path, I need about 12ns rise time to
avoid reflection, how do you think about this? The signal will come from a comparator or a flip-flop, go through a
coax cable, and a two-line I/O header, and then some
on-board trace until it reached the FPGA.

Why does a sample-hold circuit eliminate reflection and
transmission line circuit? While a sample-hold can be thought of a low-pass filter... What I can come up with is that a sample-and-hild will decrease the signal-changing rate, is that what you mean?

But a sample-and-hold makes my design complex which askes for a dedicated clock. But maybe it really addreses my problem.

SkyHigh said:

Hi greenfrog,

Both method 1 and 2 are about the same. Your cable is basically RLCG, with R and L dominating other electrical parameters with such a length like 1 ft long.

Method 1 - If you use a 1st order passive low-pass filter, it will be the similar to method 2. So you can have nth order passive or active filter. However the order here doesnt matter.

Method 2 - Adding a shunt capacitor is creating a 1st order passive low-pass filter or a series-shunt RC filter because your cable already has resistance.

From both methods you proposed, there is one thing in common, the shunt capacitance and series resistance. From any electronic design publications, one common way to reduce rise time or one common design problem that limits the rise time is shunt capacitance and series resistance.

The larger the shunt capacitance and series resistance, the longer the rise time because we know time constant = RC.
The formula for rise time (10% to 90%) is 0.63 RC.

Another method is to use a unity-gain buffer or voltage follower followed by a sample-hold circuit. Hence you can eliminate reflection and impedance mismatch on the transmission line (cable) and you can synchronise by means of a clock when you want to sample your signal from the buffer.

Click to expand...

On the driver side: Add space for a series resistor.

On the receiver side: Add space for a R-C link to GND.

The trick is to try to adjust the driver side R for the impedance of the cable. On the receiver side the R shall be ~ the impedance of the transmission line, while the C should be selected to provide a low Z for the 2ns rise time of the pulse.

Using an oscilloscope and a FET probe (= High Zin, LOW Cin) the component values should then be tweaked for lowest possible ringing.

The driver side will perhaps have current limiting output stages. This would limit the resulting current that would be needed when charging a shunt cap. Anyway this would undoubtedly put stress on the driver. If the driver output stage is not current limited, the current will have to be drawn from the power supply, and you may end up with an EMC problem.

greenfrog,

Yes. For lumped circuit RC filter at the receiver end, time constant (10 to 90%) is generally 2.2RC.

I wouldn't advise to use a FF to drive a coaxial cable that's 1ft long, as it is not designed to drive a longhaul connection.

From the information you gave in this topic, what you want is to control the rise time of the signal at the receiver end.

If your driver end is a open-collector or drain, the purpose of a unity-gain buffer that offers hi-Z input solves your impedance-matching issue. The SC after the buffer gives your the freedom to synchronise the SC and sample the signal at the output of the buffer whenever your data processing unit is ready. Since the buffer is a unity-gain buffer, it has no impact to the signal received at the input of the buffer. This offers you the ability to control when you want to signal.

Another two popular methods are T or Pi-termination network to resolve impedance-matching issue. If you want, LVDS is another method. However, they have no control of the time of flight, TOF, of the signal along the cable.

Added after 4 minutes:

2ns is considered very quick to travel on a 1ft long coaxial cable.

To drag it up to 12ns, it's not something with ordinary discrete off-the-shelve RLC components can help. You MIGHT need precision components with low tolerance or error. But 12ns is easily controlling with latching with high-speed system like FPGA.

according the voltage mode signaling , reducing the tl's euqivalent
impedance will slow the edge rate.

btw, reflection is not always a bad thing ,i think at receiver side always need some reflect to get sufficent voltage swing .