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You can refer to some DSP vlsi design books about
retiming, or sometimes this technique is also used in
datapath of uP, when deep pipeline architechture are
to be designed. but it is usualy cunstom design. some tools support it for sstandart cell based design,
what are you aiming at?
Retiming is inserting some flip-flops in the middle of your critical path to make it work over 2 cycles instead of one: that makes meeting timing easier.
You can refer to some DSP vlsi design books about
retiming, or sometimes this technique is also used in
datapath of uP, when deep pipeline architechture are
to be designed. but it is usualy cunstom design. some tools support it for sstandart cell based design,
what are you aiming at?
To reply for this , actually I am trying to design a library(full custom) so I need to know about retiming and pipelining issues.
Regards
Sandeep.
- Retiming is NOT a technique used in the STA but in Synthesis.
- Retiming(Register retiming) is a sequential optimization technique that moves registers through the combinational logic gates of a design to optimize timing and area.
- For synopsys DC tool, there are 3 kind of retiming method.
1. optimize registers: change both sequential and comb log by adding addtional DFF in paralell to the comb logic instead of just using one ( the case after the optimization with area 0 ). In such a case, the driving strength becomes stronger so we gain in timing.
2. pipeline design: in this case, the comb logic is changed by inserting the additional registers in the comb logic. The level of the pipeline is specified by the user.
3. balance registers: something like "timing borrow". By moving the DFF forwards or backwords, it borrows timing in the front or back of the DFF to satisfy the timing reqiremet at the other side.
You could refer to the Synopsys Manual (SOLD). DC part, there is a manual called "Design Compiler Reference Manual: Register Retiming" for detail.
But in practice, seldom did we use this techique. Since it will bring a lot of trouble in the verification, especially in formal verification since your formal verication tool does not know you change the structure in synthsis. I use the third part compliance verification tools. If you are using Synopsys Formal, the situataion may be better. Anyway they are from the same company, Should have some additional command to support it.
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