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For help: an analog disign question!!!

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gdhp

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hi all
In my design, i want to generate a pulse 'syn' from the 'clock' signal. After the clock is pulled down, 'syn' is pulled to high and after the clock is on, 'syn' is pulled down.( note the pll down time is long, the clock is 24MHz).

SO can anyone give me some suggestions to implement this function?
Thanks!

In my thought, i will add the clock to a low-pass filter to generate a DC value. And this DC value compare with a constant dc to generate the Pulse 'syn'.
But because the W-3db of low-pass filter is very low, so the capcitance is very large. so i want to have a change!!
 

hi btrend
would you give me some explanation?
 

1. clk = "0", I current will charge C with ΔV=I/(2*fs*C)
2. clk = "1", the nmos will clear charge voltage at C
3. if clk is toggled always, voltage at C will only get charge as (1)
if clk disappear, C serve as a integrator, with V=∫ΔV Δt, after a sufficient Δt, V should be large than Vref, so ur SYN will become high, afterthat if clk="1" again,
the NMOS will do (2) again.
do it help?
 

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    gdhp

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