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Xilinx router warning

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osbourne

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dcm may have excessive skew

When I place and route my Xilinx design, I get the following message:

WARNING:Route - CLK Net:clk_buf
may have excessive skew because 3 CLK pins
failed to route using a CLK template.

What does it mean and what can I do to optimise/circumvent this warning ?
 

Hi osbourne,

You seems to have 3 clock signals as input of your design and may be only two clock route available (buffer + global route)...
Which device do you target ?
Do you really need 3 input clock ?
 

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    osbourne

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Hi,

I have only ONE input clock in my design.
I target a Virtex II xc2v6000 device.
 

Can you post ur synthesis reports here??
 

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    osbourne

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Could you send the portion of code, wherein you have implemented the clock logic.
Have you used a clkin pin of FPGA ? If not then there may be a skew.
Have you used DCM ? If not then also there can be a skew.
Finally, have you given the clk through a BUFG ?
 

    O

    osbourne

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Hi,

yes, I have used a clkin pin of the FPGA and I have used DCM.
I think DCM automatically instantiates a BUFG.
 

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